Microchip Technology Inc. ATSAM4LS2AA 2024.06.03 ATSAM4LS2AA false ABDACB Audio Bitstream DAC ABDACB 0x0 0x0 0x400 registers n ABDACB 72 CR Control Register 0x0 32 read-write n 0x0 0x0 ALTUPR Alternative up-sampling ratio 3 1 CMOC Common mode offset control 4 1 DATAFORMAT Data word format 16 3 EN Enable 0 1 ENSelect 0 Audio DAC is disabled 0x0 1 Audio DAC is enabled 0x1 FS Sampling frequency 24 4 MONO Mono mode 5 1 SWAP Swap Channels 1 1 SWAPSelect 0 The CHANNEL0 and CHANNEL1 samples will not be swapped when writing the Audio DAC Sample Data Register (SDR) 0x0 1 The CHANNEL0 and CHANNEL1 samples will be swapped when writing the Audio DAC Sample Data Register (SDR) 0x1 SWRST Software reset 7 1 IDR Interupt Disable Register 0x18 32 write-only n 0x0 0x0 TXRDY Transmit Ready Interrupt Disable 1 1 TXRDYSelect 0 No effect 0x0 1 Disable the Audio DAC TX Ready interrupt 0x1 TXUR Transmit Underrun Interrupt Disable 2 1 TXURSelect 0 No effect 0x0 1 Disable the Audio DAC Underrun interrupt 0x1 IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 TXRDY Transmit Ready Interrupt Enable 1 1 TXRDYSelect 0 No effect 0x0 1 Enables the Audio DAC TX Ready interrupt 0x1 TXUR Transmit Underrun Interrupt Enable 2 1 TXURSelect 0 No effect 0x0 1 Enables the Audio DAC Underrun interrupt 0x1 IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 TXRDY Transmit Ready Interrupt Mask 1 1 TXRDYSelect 0 The Audio DAC TX Ready interrupt is disabled 0x0 1 The Audio DAC TX Ready interrupt is enabled 0x1 TXUR Transmit Underrun Interrupt Mask 2 1 TXURSelect 0 The Audio DAC Underrun interrupt is disabled 0x0 1 The Audio DAC Underrun interrupt is enabled 0x1 PARAMETER Parameter Register 0x28 32 read-only n 0x0 0x0 SCR Status Clear Register 0x24 32 write-only n 0x0 0x0 TXRDY Transmit Ready Interrupt Clear 1 1 TXRDYSelect 0 No effect 0x0 1 Clear the Audio DAC TX Ready interrupt 0x1 TXUR Transmit Underrun Interrupt Clear 2 1 TXURSelect 0 No effect 0x0 1 Clear the Audio DAC Underrun interrupt 0x1 SDR0 Sample Data Register 0 0x4 32 read-write n 0x0 0x0 DATA Sample Data 0 32 SDR1 Sample Data Register 1 0x8 32 read-write n 0x0 0x0 DATA Sample Data 0 32 SR Status Register 0x20 32 read-only n 0x0 0x0 BUSY ABDACB Busy 0 1 TXRDY Transmit Ready 1 1 TXRDYSelect 0 No Audio DAC TX Ready has occured since the last time ISR was read or since reset 0x0 1 At least one Audio DAC TX Ready has occured since the last time ISR was read or since reset 0x1 TXUR Transmit Underrun 2 1 TXURSelect 0 No Audio DAC Underrun has occured since the last time ISR was read or since reset 0x0 1 At least one Audio DAC Underrun has occured since the last time ISR was read or since reset 0x1 VCR0 Volume Control Register 0 0xC 32 read-write n 0x0 0x0 MUTE Mute 31 1 VOLUME Volume Control 0 15 VCR1 Volume Control Register 1 0x10 32 read-write n 0x0 0x0 MUTE Mute 31 1 VOLUME Volume Control 0 15 VERSION Version Register 0x2C 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 VERSION Version Number 0 12 ACIFC Analog Comparator Interface ACIFC 0x0 0x0 0x400 registers n ACIFC 71 CONF0 AC Configuration Register 0x1A0 32 read-write n 0x0 0x0 ALWAYSON Always On 27 1 EVENN Peripheral Event Enable Negative 16 1 EVENP Peripheral Event Enable Positive 17 1 FAST Fast Mode Enable 26 1 HYS Hysteresis Voltage Value 24 2 INSELN Negative Input Select 8 2 IS Interupt Settings 0 2 MODE Analog Comparator Mode 4 2 CONF1 AC Configuration Register 0x274 32 read-write n 0x0 0x0 ALWAYSON Always On 27 1 EVENN Peripheral Event Enable Negative 16 1 EVENP Peripheral Event Enable Positive 17 1 FAST Fast Mode Enable 26 1 HYS Hysteresis Voltage Value 24 2 INSELN Negative Input Select 8 2 IS Interupt Settings 0 2 MODE Analog Comparator Mode 4 2 CONF2 AC Configuration Register 0x34C 32 read-write n 0x0 0x0 ALWAYSON Always On 27 1 EVENN Peripheral Event Enable Negative 16 1 EVENP Peripheral Event Enable Positive 17 1 FAST Fast Mode Enable 26 1 HYS Hysteresis Voltage Value 24 2 INSELN Negative Input Select 8 2 IS Interupt Settings 0 2 MODE Analog Comparator Mode 4 2 CONF3 AC Configuration Register 0x428 32 read-write n 0x0 0x0 ALWAYSON Always On 27 1 EVENN Peripheral Event Enable Negative 16 1 EVENP Peripheral Event Enable Positive 17 1 FAST Fast Mode Enable 26 1 HYS Hysteresis Voltage Value 24 2 INSELN Negative Input Select 8 2 IS Interupt Settings 0 2 MODE Analog Comparator Mode 4 2 CONF4 AC Configuration Register 0x508 32 read-write n 0x0 0x0 ALWAYSON Always On 27 1 EVENN Peripheral Event Enable Negative 16 1 EVENP Peripheral Event Enable Positive 17 1 FAST Fast Mode Enable 26 1 HYS Hysteresis Voltage Value 24 2 INSELN Negative Input Select 8 2 IS Interupt Settings 0 2 MODE Analog Comparator Mode 4 2 CONF5 AC Configuration Register 0x5EC 32 read-write n 0x0 0x0 ALWAYSON Always On 27 1 EVENN Peripheral Event Enable Negative 16 1 EVENP Peripheral Event Enable Positive 17 1 FAST Fast Mode Enable 26 1 HYS Hysteresis Voltage Value 24 2 INSELN Negative Input Select 8 2 IS Interupt Settings 0 2 MODE Analog Comparator Mode 4 2 CONF6 AC Configuration Register 0x6D4 32 read-write n 0x0 0x0 ALWAYSON Always On 27 1 EVENN Peripheral Event Enable Negative 16 1 EVENP Peripheral Event Enable Positive 17 1 FAST Fast Mode Enable 26 1 HYS Hysteresis Voltage Value 24 2 INSELN Negative Input Select 8 2 IS Interupt Settings 0 2 MODE Analog Comparator Mode 4 2 CONF7 AC Configuration Register 0x7C0 32 read-write n 0x0 0x0 ALWAYSON Always On 27 1 EVENN Peripheral Event Enable Negative 16 1 EVENP Peripheral Event Enable Positive 17 1 FAST Fast Mode Enable 26 1 HYS Hysteresis Voltage Value 24 2 INSELN Negative Input Select 8 2 IS Interupt Settings 0 2 MODE Analog Comparator Mode 4 2 CONFW0 Window configuration Register 0x100 32 read-write n 0x0 0x0 WEVEN Window Peripheral Event Enable 11 1 WEVSRC Peripheral Event Sourse Selection for Window Mode 8 3 WFEN Window Mode Enable 16 1 WIS Window Mode Interrupt Settings 0 3 CONFW1 Window configuration Register 0x184 32 read-write n 0x0 0x0 WEVEN Window Peripheral Event Enable 11 1 WEVSRC Peripheral Event Sourse Selection for Window Mode 8 3 WFEN Window Mode Enable 16 1 WIS Window Mode Interrupt Settings 0 3 CONFW2 Window configuration Register 0x20C 32 read-write n 0x0 0x0 WEVEN Window Peripheral Event Enable 11 1 WEVSRC Peripheral Event Sourse Selection for Window Mode 8 3 WFEN Window Mode Enable 16 1 WIS Window Mode Interrupt Settings 0 3 CONFW3 Window configuration Register 0x298 32 read-write n 0x0 0x0 WEVEN Window Peripheral Event Enable 11 1 WEVSRC Peripheral Event Sourse Selection for Window Mode 8 3 WFEN Window Mode Enable 16 1 WIS Window Mode Interrupt Settings 0 3 CTRL Control Register 0x0 32 read-write n 0x0 0x0 ACTEST Analog Comparator Test Mode 7 1 EN ACIFC Enable 0 1 ESTART Peripheral Event Start Single Comparison 5 1 EVENTEN Peripheral Event Trigger Enable 1 1 USTART User Start Single Comparison 4 1 ICR Interrupt Status Clear Register 0x20 32 write-only n 0x0 0x0 ACINT0 AC0 Interrupt Status Clear 0 1 write-only ACINT1 AC1 Interrupt Status Clear 2 1 write-only ACINT2 AC2 Interrupt Status Clear 4 1 write-only ACINT3 AC3 Interrupt Status Clear 6 1 write-only ACINT4 AC4 Interrupt Status Clear 8 1 write-only ACINT5 AC5 Interrupt Status Clear 10 1 write-only ACINT6 AC6 Interrupt Status Clear 12 1 write-only ACINT7 AC7 Interrupt Status Clear 14 1 write-only SUTINT0 AC0 Startup Time Interrupt Status Clear 1 1 write-only SUTINT1 AC1 Startup Time Interrupt Status Clear 3 1 write-only SUTINT2 AC2 Startup Time Interrupt Status Clear 5 1 write-only SUTINT3 AC3 Startup Time Interrupt Status Clear 7 1 write-only SUTINT4 AC4 Startup Time Interrupt Status Clear 9 1 write-only SUTINT5 AC5 Startup Time Interrupt Status Clear 11 1 write-only SUTINT6 AC6 Startup Time Interrupt Status Clear 13 1 write-only SUTINT7 AC7 Startup Time Interrupt Status Clear 15 1 write-only WFINT0 Window0 Mode Interrupt Status Clear 24 1 write-only WFINT1 Window1 Mode Interrupt Status Clear 25 1 write-only WFINT2 Window2 Mode Interrupt Status Clear 26 1 write-only WFINT3 Window3 Mode Interrupt Status Clear 27 1 write-only IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 ACINT0 AC0 Interrupt Disable 0 1 write-only ACINT1 AC1 Interrupt Disable 2 1 write-only ACINT2 AC2 Interrupt Disable 4 1 write-only ACINT3 AC3 Interrupt Disable 6 1 write-only ACINT4 AC4 Interrupt Disable 8 1 write-only ACINT5 AC5 Interrupt Disable 10 1 write-only ACINT6 AC6 Interrupt Disable 12 1 write-only ACINT7 AC7 Interrupt Disable 14 1 write-only SUTINT0 AC0 Startup Time Interrupt Disable 1 1 write-only SUTINT1 AC1 Startup Time Interrupt Disable 3 1 write-only SUTINT2 AC2 Startup Time Interrupt Disable 5 1 write-only SUTINT3 AC3 Startup Time Interrupt Disable 7 1 write-only SUTINT4 AC4 Startup Time Interrupt Disable 9 1 write-only SUTINT5 AC5 Startup Time Interrupt Disable 11 1 write-only SUTINT6 AC6 Startup Time Interrupt Disable 13 1 write-only SUTINT7 AC7 Startup Time Interrupt Disable 15 1 write-only WFINT0 Window0 Mode Interrupt Disable 24 1 write-only WFINT1 Window1 Mode Interrupt Disable 25 1 write-only WFINT2 Window2 Mode Interrupt Disable 26 1 write-only WFINT3 Window3 Mode Interrupt Disable 27 1 write-only IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 ACINT0 AC0 Interrupt Enable 0 1 write-only ACINT1 AC1 Interrupt Enable 2 1 write-only ACINT2 AC2 Interrupt Enable 4 1 write-only ACINT3 AC3 Interrupt Enable 6 1 write-only ACINT4 AC4 Interrupt Enable 8 1 write-only ACINT5 AC5 Interrupt Enable 10 1 write-only ACINT6 AC6 Interrupt Enable 12 1 write-only ACINT7 AC7 Interrupt Enable 14 1 write-only SUTINT0 AC0 Startup Time Interrupt Enable 1 1 write-only SUTINT1 AC1 Startup Time Interrupt Enable 3 1 write-only SUTINT2 AC2 Startup Time Interrupt Enable 5 1 write-only SUTINT3 AC3 Startup Time Interrupt Enable 7 1 write-only SUTINT4 AC4 Startup Time Interrupt Enable 9 1 write-only SUTINT5 AC5 Startup Time Interrupt Enable 11 1 write-only SUTINT6 AC6 Startup Time Interrupt Enable 13 1 write-only SUTINT7 AC7 Startup Time Interrupt Enable 15 1 write-only WFINT0 Window0 Mode Interrupt Enable 24 1 write-only WFINT1 Window1 Mode Interrupt Enable 25 1 write-only WFINT2 Window2 Mode Interrupt Enable 26 1 write-only WFINT3 Window3 Mode Interrupt Enable 27 1 write-only IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 ACINT0 AC0 Interrupt Mask 0 1 read-only ACINT1 AC1 Interrupt Mask 2 1 read-only ACINT2 AC2 Interrupt Mask 4 1 read-only ACINT3 AC3 Interrupt Mask 6 1 read-only ACINT4 AC4 Interrupt Mask 8 1 read-only ACINT5 AC5 Interrupt Mask 10 1 read-only ACINT6 AC6 Interrupt Mask 12 1 read-only ACINT7 AC7 Interrupt Mask 14 1 read-only SUTINT0 AC0 Startup Time Interrupt Mask 1 1 read-only SUTINT1 AC1 Startup Time Interrupt Mask 3 1 read-only SUTINT2 AC2 Startup Time Interrupt Mask 5 1 read-only SUTINT3 AC3 Startup Time Interrupt Mask 7 1 read-only SUTINT4 AC4 Startup Time Interrupt Mask 9 1 read-only SUTINT5 AC5 Startup Time Interrupt Mask 11 1 read-only SUTINT6 AC6 Startup Time Interrupt Mask 13 1 read-only SUTINT7 AC7 Startup Time Interrupt Mask 15 1 read-only WFINT0 Window0 Mode Interrupt Mask 24 1 read-only WFINT1 Window1 Mode Interrupt Mask 25 1 read-only WFINT2 Window2 Mode Interrupt Mask 26 1 read-only WFINT3 Window3 Mode Interrupt Mask 27 1 read-only ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 ACINT0 AC0 Interrupt Status 0 1 read-only ACINT1 AC1 Interrupt Status 2 1 read-only ACINT2 AC2 Interrupt Status 4 1 read-only ACINT3 AC3 Interrupt Status 6 1 read-only ACINT4 AC4 Interrupt Status 8 1 read-only ACINT5 AC5 Interrupt Status 10 1 read-only ACINT6 AC6 Interrupt Status 12 1 read-only ACINT7 AC7 Interrupt Status 14 1 read-only SUTINT0 AC0 Startup Time Interrupt Status 1 1 read-only SUTINT1 AC1 Startup Time Interrupt Status 3 1 read-only SUTINT2 AC2 Startup Time Interrupt Status 5 1 read-only SUTINT3 AC3 Startup Time Interrupt Status 7 1 read-only SUTINT4 AC4 Startup Time Interrupt Status 9 1 read-only SUTINT5 AC5 Startup Time Interrupt Status 11 1 read-only SUTINT6 AC6 Startup Time Interrupt Status 13 1 read-only SUTINT7 AC7 Startup Time Interrupt Status 15 1 read-only WFINT0 Window0 Mode Interrupt Status 24 1 read-only WFINT1 Window1 Mode Interrupt Status 25 1 read-only WFINT2 Window2 Mode Interrupt Status 26 1 read-only WFINT3 Window3 Mode Interrupt Status 27 1 read-only PARAMETER Parameter Register 0x30 32 read-only n 0x0 0x0 ACIMPL0 Analog Comparator 0 Implemented 0 1 read-only ACIMPL1 Analog Comparator 1 Implemented 1 1 read-only ACIMPL2 Analog Comparator 2 Implemented 2 1 read-only ACIMPL3 Analog Comparator 3 Implemented 3 1 read-only ACIMPL4 Analog Comparator 4 Implemented 4 1 read-only ACIMPL5 Analog Comparator 5 Implemented 5 1 read-only ACIMPL6 Analog Comparator 6 Implemented 6 1 read-only ACIMPL7 Analog Comparator 7 Implemented 7 1 read-only WIMPL0 Window0 Mode Implemented 16 1 read-only WIMPL1 Window1 Mode Implemented 17 1 read-only WIMPL2 Window2 Mode Implemented 18 1 read-only WIMPL3 Window3 Mode Implemented 19 1 read-only SR Status Register 0x4 32 read-only n 0x0 0x0 ACCS0 AC0 Current Comparison Status 0 1 read-only ACCS1 AC1 Current Comparison Status 2 1 read-only ACCS2 AC2 Current Comparison Status 4 1 read-only ACCS3 AC3 Current Comparison Status 6 1 read-only ACCS4 AC4 Current Comparison Status 8 1 read-only ACCS5 AC5 Current Comparison Status 10 1 read-only ACCS6 AC6 Current Comparison Status 12 1 read-only ACCS7 AC7 Current Comparison Status 14 1 read-only ACRDY0 AC0 Ready 1 1 read-only ACRDY1 AC1 Ready 3 1 read-only ACRDY2 AC2 Ready 5 1 read-only ACRDY3 AC3 Ready 7 1 read-only ACRDY4 AC4 Ready 9 1 read-only ACRDY5 AC5 Ready 11 1 read-only ACRDY6 AC6 Ready 13 1 read-only ACRDY7 AC7 Ready 15 1 read-only WFCS0 Window0 Mode Current Status 24 1 read-only WFCS1 Window1 Mode Current Status 25 1 read-only WFCS2 Window2 Mode Current Status 26 1 read-only WFCS3 Window3 Mode Current Status 27 1 read-only TR Test Register 0x24 32 read-write n 0x0 0x0 ACTEST0 AC0 Output Override Value 0 1 ACTEST1 AC1 Output Override Value 1 1 ACTEST2 AC2 Output Override Value 2 1 ACTEST3 AC3 Output Override Value 3 1 ACTEST4 AC4 Output Override Value 4 1 ACTEST5 AC5 Output Override Value 5 1 ACTEST6 AC6 Output Override Value 6 1 ACTEST7 AC7 Output Override Value 7 1 VERSION Version Register 0x34 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only ADCIFE ADC controller interface ADCIFE 0x0 0x0 0x400 registers n ADCIFE 69 CALIB Calibration Register 0x3C 32 read-write n 0x0 0x0 BIASCAL Bias Calibration 12 4 BIASSEL Select bias mode 8 1 CALIB Calibration Value 0 8 FCD Flash Calibration Done 16 1 CDMA Configuration Direct Memory Access Register FIRST_DMA_WORD 0x18 32 write-only n 0x0 0x0 BIPOLAR Bipolar Mode 2 1 write-only DW Double Word transmitting 31 1 write-only ENSTUP Enable Start-Up Time 8 1 write-only GAIN Gain factor 4 3 write-only GCOMP Gain Compensation 7 1 write-only HWLA Half word left adjust 0 1 write-only INTERNAL Internal Voltage Source Selection 14 2 write-only MUXNEG MUX selection on Negative ADC input channel 20 3 MUXPOS MUX selection on Positive ADC input channel 16 4 write-only RES Resolution 12 1 write-only STRIG Sequencer Trigger Event 3 1 write-only TSS Internal timer start or stop bit 13 1 write-only ZOOMRANGE Zoom shift/unipolar reference source selection 28 3 write-only CFG Configuration Register 0x4 32 read-write n 0x0 0x0 CLKSEL Clock Selection for sequencer/ADC cell 6 1 PRESCAL Prescaler Rate Selection 8 3 REFSEL ADC Reference Selection 1 3 SPEED ADC current reduction 4 2 CR Control Register 0x0 32 write-only n 0x0 0x0 BGREQDIS Bandgap buffer request disable 11 1 write-only BGREQEN Bandgap buffer request enable 10 1 write-only DIS ADCIFD disable 9 1 write-only EN ADCIFD enable 8 1 write-only REFBUFDIS Reference buffer disable 5 1 write-only REFBUFEN Reference buffer enable 4 1 write-only STRIG Sequencer trigger 3 1 write-only SWRST Software reset 0 1 write-only TSTART Internal timer start bit 2 1 write-only TSTOP Internal timer stop bit 1 1 write-only IDR Interrupt Disable Register 0x34 32 write-only n 0x0 0x0 LOVR Sequencer last converted value overrun Interrupt Disable 1 1 write-only SEOC Sequencer end of conversion Interrupt Disable 0 1 write-only SMTRG Sequencer missed trigger event Interrupt Disable 3 1 write-only TTO Timer time-out Interrupt Disable 5 1 write-only WM Window monitor Interrupt Disable 2 1 write-only IER Interrupt Enable Register 0x30 32 write-only n 0x0 0x0 LOVR Sequencer last converted value overrun Interrupt Enable 1 1 write-only SEOC Sequencer end of conversion Interrupt Enable 0 1 write-only SMTRG Sequencer missed trigger event Interrupt Enable 3 1 write-only TTO Timer time-out Interrupt Enable 5 1 write-only WM Window monitor Interrupt Enable 2 1 write-only IMR Interrupt Mask Register 0x38 32 read-only n 0x0 0x0 LOVR Sequencer last converted value overrun Interrupt Mask 1 1 read-only SEOC Sequencer end of conversion Interrupt Mask 0 1 read-only SMTRG Sequencer missed trigger event Interrupt Mask 3 1 read-only TTO Timer time-out Interrupt Mask 5 1 read-only WM Window monitor Interrupt Mask 2 1 read-only ITIMER Internal Timer Register 0x20 32 read-write n 0x0 0x0 ITMC Internal timer max counter 0 16 LCV Sequencer Last Converted Value Register 0x2C 32 read-only n 0x0 0x0 LCNC Last converted negative channel 20 3 read-only LCPC Last converted positive channel 16 4 read-only LCV Last converted value 0 16 read-only PARAMETER Parameter Register 0x44 32 read-only n 0x0 0x0 N Number of channels 0 8 read-only RTS Resistive Touch Screen Register 0x10 32 read-write n 0x0 0x0 SCR Status Clear Register 0xC 32 write-only n 0x0 0x0 LOVR Sequencer last converted value overrun 1 1 write-only SEOC Sequencer end of conversion 0 1 write-only SMTRG Sequencer missed trigger event 3 1 write-only SUTD Start-up time done 4 1 write-only TTO Timer time-out 5 1 write-only WM Window monitor 2 1 write-only SEQCFG Sequencer Configuration Register 0x14 32 read-write n 0x0 0x0 BIPOLAR Bipolar Mode 2 1 GAIN Gain factor 4 3 GCOMP Gain Compensation 7 1 HWLA Half word left adjust 0 1 INTERNAL Internal Voltage Source Selection 14 2 MUXNEG MUX selection on Negative ADC input channel 20 3 MUXPOS MUX selection on Positive ADC input channel 16 4 RES Resolution 12 1 TRGSEL Trigger selection 8 3 ZOOMRANGE Zoom shift/unipolar reference source selection 28 3 SR Status Register 0x8 32 read-only n 0x0 0x0 CBUSY Conversion busy 27 1 read-only EN Enable Status 24 1 read-only LOVR Sequencer last converted value overrun 1 1 read-only REFBUF Reference buffer status 28 1 read-only SBUSY Sequencer busy 26 1 read-only SEOC Sequencer end of conversion 0 1 read-only SMTRG Sequencer missed trigger event 3 1 read-only SUTD Start-up time done 4 1 read-only TBUSY Timer busy 25 1 read-only TTO Timer time-out 5 1 read-only WM Window monitor 2 1 read-only TIM Timing Configuration Register 0x1C 32 read-write n 0x0 0x0 ENSTUP Enable Startup 8 1 STARTUP Startup time 0 5 VERSION Version Register 0x40 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 read-only VERSION Version number 0 12 read-only WCFG Window Monitor Configuration Register 0x24 32 read-write n 0x0 0x0 WM Window Monitor Mode 12 3 WTH Window Monitor Threshold Configuration Register 0x28 32 read-write n 0x0 0x0 HT High Threshold 16 12 LT Low threshold 0 12 AST Asynchronous Timer AST 0x0 0x0 0x400 registers n AST_ALARM 39 AST_PER 40 AST_OVF 41 AST_READY 42 AST_CLKREADY 43 AR0 Alarm Register 0 0x20 32 read-write n 0x0 0x0 VALUE Alarm Value 0 32 AR1 Alarm Register 1 0x24 32 read-write n 0x0 0x0 VALUE Alarm Value 0 32 CALV Calendar Value 0x54 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 MIN Minute 6 6 MONTH Month 22 4 SEC Second 0 6 YEAR Year 26 6 CLOCK Clock Control Register 0x40 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 CENSelect 0 The clock is disabled 0x0 1 The clock is enabled 0x1 CSSEL Clock Source Selection 8 3 CSSELSelect SLOWCLOCK Slow clock 0x0 32KHZCLK 32 kHz clock 0x1 PBCLOCK PB clock 0x2 GCLK Generic clock 0x3 1KHZCLK 1kHz clock from 32 kHz oscillator 0x4 CR Control Register 0x0 32 read-write n 0x0 0x0 CA0 Clear on Alarm 0 8 1 CA1 Clear on Alarm 1 9 1 CAL Calendar mode 2 1 EN Enable 0 1 ENSelect 0 The AST is disabled. 0x0 1 The AST is enabled 0x1 PCLR Prescaler Clear 1 1 PSEL Prescaler Select 16 5 CV Counter Value 0x4 32 read-write n 0x0 0x0 VALUE AST Value 0 32 DTR Digital Tuner Register 0x44 32 read-write n 0x0 0x0 ADD ADD 5 1 EXP EXP 0 5 VALUE VALUE 8 8 EVD Event Disable Register 0x4C 32 write-only n 0x0 0x0 ALARM0 Alarm 0 8 1 write-only ALARM1 Alarm 1 9 1 write-only OVF Overflow 0 1 write-only PER0 Perioidc 0 16 1 write-only PER1 Periodic 1 17 1 write-only EVE Event Enable Register 0x48 32 write-only n 0x0 0x0 ALARM0 Alarm 0 8 1 write-only ALARM1 Alarm 1 9 1 write-only OVF Overflow 0 1 write-only PER0 Perioidc 0 16 1 write-only PER1 Periodic 1 17 1 write-only EVM Event Mask Register 0x50 32 read-only n 0x0 0x0 ALARM0 Alarm 0 8 1 read-only ALARM1 Alarm 1 9 1 read-only OVF Overflow 0 1 read-only PER0 Perioidc 0 16 1 read-only PER1 Periodic 1 17 1 read-only IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 ALARM0 Alarm 0 8 1 write-only ALARM0Select 0 No effect 0x0 1 Disable interrupt 0x1 ALARM1 Alarm 1 9 1 write-only ALARM1Select 0 No effect 0x0 1 Disable interrupt 0x1 CLKRDY Clock Ready 29 1 write-only CLKRDYSelect 0 No effect 0x0 1 Disable interrupt 0x1 OVF Overflow 0 1 write-only OVFSelect 0 No effect 0x0 1 Disable Interrupt. 0x1 PER0 Periodic 0 16 1 write-only PER0Select 0 No effet 0x0 1 Disalbe interrupt 0x1 PER1 Periodic 1 17 1 write-only PER1Select 0 No effect 0x0 1 Disable interrupt 0x1 READY AST Ready 25 1 write-only READYSelect 0 No effect 0x0 1 Disable interrupt 0x1 IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 ALARM0 Alarm 0 8 1 write-only ALARM0Select 0 No effect 0x0 1 Enable interrupt 0x1 ALARM1 Alarm 1 9 1 write-only ALARM1Select 0 No effect 0x0 1 Enable interrupt 0x1 CLKRDY Clock Ready 29 1 write-only CLKRDYSelect 0 No effect 0x0 1 Enable interrupt 0x1 OVF Overflow 0 1 write-only OVFSelect 0 No effect 0x0 1 Enable Interrupt. 0x1 PER0 Periodic 0 16 1 write-only PER0Select 0 No effect 0x0 1 Enable interrupt 0x1 PER1 Periodic 1 17 1 write-only PER1Select 0 No effect 0x0 1 Enable interrupt 0x1 READY AST Ready 25 1 write-only READYSelect 0 No effect 0x0 1 Enable interrupt 0x1 IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 ALARM0 Alarm 0 8 1 read-only ALARM0Select 0 Interupt is disabled 0x0 1 Interrupt is enabled 0x1 ALARM1 Alarm 1 9 1 read-only ALARM1Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled 0x1 CLKRDY Clock Ready 29 1 read-only CLKRDYSelect 0 Interrupt is disabled 0x0 1 Interrupt is enabled 0x1 OVF Overflow 0 1 read-only OVFSelect 0 Interrupt is disabled 0x0 1 Interrupt is enabled. 0x1 PER0 Periodic 0 16 1 read-only PER0Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled 0x1 PER1 Periodic 1 17 1 read-only PER1Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled 0x1 READY AST Ready 25 1 read-only READYSelect 0 Interrupt is disabled 0x0 1 Interrupt is enabled 0x1 PARAMETER Parameter Register 0xF0 32 read-only n 0x0 0x0 DT Digital Tuner 0 1 read-only DTSelect OFF Digital tuner off 0x0 ON Digital tuner on 0x1 DTEXPVALUE Digital Tuner Exponent Value 2 5 read-only DTEXPWA Digital Tuner Exponent Writeable 1 1 read-only DTEXPWASelect 0 Digital tuner exponent is a constant value. Writes to EXP bitfield in DTR will be discarded. 0x0 1 Digital tuner exponent is chosen by writing to EXP bitfield in DTR 0x1 NUMAR Number of alarm comparators 8 2 read-only NUMARSelect ZERO No alarm comparators 0x0 ONE One alarm comparator 0x1 TWO Two alarm comparators 0x2 NUMPIR Number of periodic comparators 12 1 read-only NUMPIRSelect ONE One periodic comparator 0x0 TWO Two periodic comparators 0x1 PER0VALUE Periodic Interval 0 Value 16 5 read-only PER1VALUE Periodic Interval 1 Value 24 5 read-only PIR0WA Periodic Interval 0 Writeable 14 1 read-only PIR0WASelect 0 Periodic alarm prescaler 0 tapping is a constant value. Writes to INSEL bitfield in PIR0 will be discarded. 0x0 1 Periodic alarm prescaler 0 tapping is chosen by writing to INSEL bitfield in PIR0 0x1 PIR1WA Periodic Interval 1 Writeable 15 1 read-only PIR1WASelect 0 Writes to PIR1 will be discarded 0x0 1 PIR1 can be written 0x1 PIR0 Periodic Interval Register 0 0x30 32 read-write n 0x0 0x0 INSEL Interval Select 0 5 PIR1 Periodic Interval Register 1 0x34 32 read-write n 0x0 0x0 INSEL Interval Select 0 5 SCR Status Clear Register 0xC 32 write-only n 0x0 0x0 ALARM0 Alarm 0 8 1 write-only ALARM1 Alarm 1 9 1 write-only CLKRDY Clock Ready 29 1 write-only OVF Overflow 0 1 write-only PER0 Periodic 0 16 1 write-only PER1 Periodic 1 17 1 write-only READY AST Ready 25 1 write-only SR Status Register 0x8 32 read-only n 0x0 0x0 ALARM0 Alarm 0 8 1 read-only ALARM1 Alarm 1 9 1 read-only BUSY AST Busy 24 1 read-only BUSYSelect 0 The AST accepts writes to CV, WER, DTR, SCR, AR, PIR and CR 0x0 1 The AST is busy and will discard writes to CV, WER, DTR, SCR, AR, PIR and CR 0x1 CLKBUSY Clock Busy 28 1 read-only CLKBUSYSelect 0 The clock is ready and can be changed 0x0 1 CEN has been written and the clock is busy 0x1 CLKRDY Clock Ready 29 1 read-only OVF Overflow 0 1 read-only PER0 Periodic 0 16 1 read-only PER1 Periodic 1 17 1 read-only READY AST Ready 25 1 read-only VERSION Version Register 0xFC 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only WER Wake Enable Register 0x1C 32 read-write n 0x0 0x0 ALARM0 Alarm 0 8 1 ALARM0Select 0 The corresponing event will not wake up the CPU from sleep mode 0x0 1 The corresponding event will wake up the CPU from sleep mode 0x1 ALARM1 Alarm 1 9 1 ALARM1Select 0 The corresponing event will not wake up the CPU from sleep mode 0x0 1 The corresponding event will wake up the CPU from sleep mode 0x1 OVF Overflow 0 1 OVFSelect 0 The corresponing event will not wake up the CPU from sleep mode 0x0 1 The corresponding event will wake up the CPU from sleep mode 0x1 PER0 Periodic 0 16 1 PER0Select 0 The corresponing event will not wake up the CPU from sleep mode 0x0 1 The corresponding event will wake up the CPU from sleep mode 0x1 PER1 Periodic 1 17 1 PER1Select 0 The corresponing event will not wake up the CPU from sleep mode 0x0 1 The corresponding event will wake up the CPU from sleep mode 0x1 BPM Backup Power Manager BPM 0x0 0x0 0x400 registers n BPM 37 BKUPPMUX Backup Pin Muxing Register 0x30 32 read-write n 0x0 0x0 BKUPPMUX Backup Pin Muxing 0 9 BKUPWCAUSE Backup Wake up Cause Register 0x28 32 read-only n 0x0 0x0 BKUPWEN Backup Wake up Enable Register 0x2C 32 read-write n 0x0 0x0 BPR Bypass Register 0x40 32 read-write n 0x0 0x0 BIASSEN Bias Switch Enable 6 1 BOD18CONT BOD18 in continuous mode not disabled in WAIT/RET/BACKUP modes 8 1 DLYRSTD Delaying Reset Disable 5 1 FBRDYEN Flash Bias Ready Enable 11 1 FFFW Force Flash Fast Wakeup 10 1 FVREFSEN Flash Vref Switch Enable 12 1 LATSEN Latdel Switch Enable 7 1 POBS Pico Uart Observability 9 1 PSBTD Power Scaling Bias Timing Disable 3 1 PSHFD Power Scaling Halt Flash Until VREGOK Disable 4 1 PSMPSPB Power Save Mode Power Scaling Preset Bypass 1 1 RUNPSPB Run Mode Power Scaling Preset Bypass 0 1 SEQSTN Sequencial Startup from ULP (Active Low) 2 1 FWPSAVEPS Factory Word Power Save PS Register 0x48 32 read-only n 0x0 0x0 BREGLEVEL Backup mode Regulator Level 26 4 read-only FWSAS Flash Wait State Automatic Switching 31 1 read-only POR18DIS POR 18 Disable 30 1 read-only RBIAS Bias in Retention mode 17 4 read-only RLATDEL Flash Latdel in Retention mode 21 5 read-only RREGLEVEL Retention mode Regulator Level 13 4 read-only WBIAS Bias in wait mode 4 4 read-only WLATDEL Flash Latdel in wait mode 8 5 read-only WREGLEVEL Wait mode Regulator Level 0 4 read-only FWRUNPS Factory Word Run PS Register 0x44 32 read-only n 0x0 0x0 FLASHBIAS Flash Bias Value 13 4 FLASHLATDEL Flash Latch Delay Value 8 5 FPPW Flash Pico Power Mode 17 1 RC115 RC 115KHZ Calibration Value 18 7 RCFAST RCFAST Calibration Value 25 7 REFTYPE Reference Type 6 2 REFTYPESelect BOTH None 0x0 BG None 0x1 LPBG None 0x2 INTERNAL None 0x3 REGLEVEL Regulator Voltage Level 0 4 REGTYPE Regulator Type 4 2 REGTYPESelect NORMAL None 0x0 LP None 0x1 XULP None 0x2 ICR Interrupt Clear Register 0x10 32 write-only n 0x0 0x0 AE Access Error Interrupt Status Clear 31 1 write-only PSOK Power Scaling OK Interrupt Status Clear 0 1 write-only IDR Interrupt Disable Register 0x4 32 write-only n 0x0 0x0 AE Access Error Interrupt Disable 31 1 write-only PSOK Power Scaling OK Interrupt Disable 0 1 write-only IER Interrupt Enable Register 0x0 32 write-only n 0x0 0x0 AE Access Error Interrupt Enable 31 1 write-only PSOK Power Scaling OK Interrupt Enable 0 1 write-only IMR Interrupt Mask Register 0x8 32 read-only n 0x0 0x0 AE Access Error Interrupt Mask 31 1 read-only PSOK Power Scaling OK Interrupt Mask 0 1 read-only IORET Input Output Retention Register 0x34 32 read-write n 0x0 0x0 RET Retention on I/O lines after waking up from the BACKUP mode 0 1 ISR Interrupt Status Register 0xC 32 read-only n 0x0 0x0 AE Access Error Interrupt Status 31 1 read-only PSOK Power Scaling OK Interrupt Status 0 1 read-only PMCON Power Mode Control Register 0x1C 32 read-write n 0x0 0x0 BKUP BACKUP Mode 8 1 CK32S 32Khz-1Khz Clock Source Selection 16 1 FASTWKUP Fast Wakeup 24 1 PS Power Scaling Configuration Value 0 2 PSCM Power Scaling Change Mode 3 1 PSCREQ Power Scaling Change Request 2 1 RET RETENTION Mode 9 1 SLEEP SLEEP mode Configuration 12 2 SR Status Register 0x14 32 read-only n 0x0 0x0 PSOK Power Scaling OK Status 0 1 read-only UNLOCK Unlock Register 0x18 32 write-only n 0x0 0x0 ADDR Unlock Address 0 10 write-only KEY Unlock Key 24 8 write-only VERSION Version Register 0xFC 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only BSCIF Backup System Control Interface BSCIF 0x0 0x0 0x400 registers n BSCIF 38 BGCR Bandgap Calibration Register 0x5C 32 read-write n 0x0 0x0 BGCTRL Bandgap Control Register 0x60 32 read-write n 0x0 0x0 ADCISEL ADC Input Selection 0 2 ADCISELSelect DIS None 0x0 VTEMP None 0x1 VREF None 0x2 TSEN Temperature Sensor Enable 8 1 BGREFIFBVERSION BGREFIFB Version Register 0x3E8 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only BGSR Bandgap Status Register 0x64 32 read-only n 0x0 0x0 BGBUFRDY Bandgap Buffer Ready 0 8 read-only BGBUFRDYSelect FLASH None 0x1 ADC None 0x10 PLL None 0x2 LCD None 0x20 VREG None 0x4 BUFRR None 0x8 BGRDY Bandgap Voltage Reference Ready 16 1 read-only LPBGRDY Low Power Bandgap Voltage Reference Ready 17 1 read-only VREF Voltage Reference Used by the System 18 2 read-only BOD18CTRL BOD18 Control Register 0x38 32 read-write n 0x0 0x0 ACTION Action 8 2 EN Enable 0 1 FCD BOD Fuse Calibration Done 30 1 HYST BOD Hysteresis 1 1 MODE Operation modes 16 1 SFV BOD Control Register Store Final Value 31 1 BOD18LEVEL BOD18 Level Register 0x3C 32 read-write n 0x0 0x0 RANGE BOD Threshold Range 31 1 VAL BOD Value 0 6 BOD33CTRL BOD33 Control Register 0x2C 32 read-write n 0x0 0x0 ACTION Action 8 2 EN Enable 0 1 FCD BOD Fuse Calibration Done 30 1 HYST BOD Hysteresis 1 1 MODE Operation modes 16 1 SFV BOD Control Register Store Final Value 31 1 BOD33LEVEL BOD33 Level Register 0x30 32 read-write n 0x0 0x0 VAL BOD Value 0 6 BOD33SAMPLING BOD33 Sampling Control Register 0x34 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 CSSEL Clock Source Select 1 1 PSEL Prescaler Select 8 4 BODIFCVERSION BODIFC Version Register 0x3F0 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 VERSION Version Number 0 12 BR0 Backup Register 0xF0 32 read-write n 0x0 0x0 BR1 Backup Register 0x16C 32 read-write n 0x0 0x0 BR2 Backup Register 0x1EC 32 read-write n 0x0 0x0 BR3 Backup Register 0x270 32 read-write n 0x0 0x0 BRIFBVERSION Backup Register Interface Version Register 0x3E4 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 VERSION Version Number 0 12 CSCR Chip Specific Configuration Register 0x1C 32 read-write n 0x0 0x0 ICR Interrupt Clear Register 0x10 32 write-only n 0x0 0x0 AE Access Error 31 1 write-only BOD18DET BOD18 Detected 6 1 write-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 write-only BOD33DET BOD33 Detected 5 1 write-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 write-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 write-only OSC32RDY 32kHz Oscillator Ready 0 1 write-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 write-only RC32KRDY 32kHz RC Oscillator Ready 1 1 write-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 write-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 write-only SSWRDY VREG Stop Switching Ready 9 1 write-only VREGOK Main VREG OK 10 1 write-only IDR Interrupt Disable Register 0x4 32 write-only n 0x0 0x0 AE Access Error 31 1 write-only BOD18DET BOD18 Detected 6 1 write-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 write-only BOD33DET BOD33 Detected 5 1 write-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 write-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 write-only OSC32RDY 32kHz Oscillator Ready 0 1 write-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 write-only RC32KRDY 32kHz RC Oscillator Ready 1 1 write-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 write-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 write-only SSWRDY VREG Stop Switching Ready 9 1 write-only VREGOK Mai n VREG OK 10 1 write-only IER Interrupt Enable Register 0x0 32 write-only n 0x0 0x0 AE Access Error 31 1 write-only BOD18DET BOD18 Detected 6 1 write-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 write-only BOD33DET BOD33 Detected 5 1 write-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 write-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 write-only OSC32RDY 32kHz Oscillator Ready 0 1 write-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 write-only RC32KRDY 32kHz RC Oscillator Ready 1 1 write-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 write-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 write-only SSWRDY VREG Stop Switching Ready 9 1 write-only VREGOK Main VREG OK 10 1 write-only IMR Interrupt Mask Register 0x8 32 read-only n 0x0 0x0 AE Access Error 31 1 read-only BOD18DET BOD18 Detected 6 1 read-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 read-only BOD33DET BOD33 Detected 5 1 read-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 read-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 read-only OSC32RDY 32kHz Oscillator Ready 0 1 read-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 read-only RC32KRDY 32kHz RC Oscillator Ready 1 1 read-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 read-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 read-only SSWRDY VREG Stop Switching Ready 9 1 read-only VREGOK Main VREG OK 10 1 read-only ISR Interrupt Status Register 0xC 32 read-only n 0x0 0x0 AE Access Error 31 1 read-only BOD18DET BOD18 Detected 6 1 read-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 read-only BOD33DET BOD33 Detected 5 1 read-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 read-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 read-only OSC32RDY 32kHz Oscillator Ready 0 1 read-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 read-only RC32KRDY 32kHz RC Oscillator Ready 1 1 read-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 read-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 read-only SSWRDY VREG Stop Switching Ready 9 1 read-only VREGOK Main VREG OK 10 1 read-only OSC32IFAVERSION 32 KHz Oscillator Version Register 0x3F8 32 read-only n 0x0 0x0 VARIANT Variant nubmer 16 4 VERSION Version number 0 12 OSCCTRL32 Oscillator 32 Control Register 0x20 32 read-write n 0x0 0x0 EN1K 1 KHz output Enable 3 1 EN32K 32 KHz output Enable 2 1 MODE Oscillator Mode 8 3 OSC32EN 32 KHz Oscillator Enable 0 1 PINSEL Pins Select 1 1 SELCURR Current selection 12 4 STARTUP Oscillator Start-up Time 16 3 PCLKSR Power and Clocks Status Register 0x14 32 read-only n 0x0 0x0 BOD18DET BOD18 Detected 6 1 read-only BOD18SYNRDY BOD18 Synchronization Ready 8 1 read-only BOD33DET BOD33 Detected 5 1 read-only BOD33SYNRDY BOD33 Synchronization Ready 7 1 read-only LPBGRDY Low Power Bandgap Voltage Reference Ready 12 1 read-only OSC32RDY 32kHz Oscillator Ready 0 1 read-only RC1MRDY RC 1MHz Oscillator Ready 11 1 read-only RC32KLOCK 32kHz RC Oscillator Lock 2 1 read-only RC32KRDY 32kHz RC Oscillator Ready 1 1 read-only RC32KREFE 32kHz RC Oscillator Reference Error 3 1 read-only RC32KSAT 32kHz RC Oscillator Saturation 4 1 read-only SSWRDY VREG Stop Switching Ready 9 1 read-only VREGOK Main VREG OK 10 1 read-only RC1MCR 1MHz RC Clock Configuration Register 0x58 32 read-write n 0x0 0x0 CLKCAL 1MHz RC Osc Calibration 8 5 CLKOE 1MHz RC Osc Clock Output Enable 0 1 FCD Flash Calibration Done 7 1 RC32KCR 32 kHz RC Oscillator Control Register 0x24 32 read-write n 0x0 0x0 EN Enable as Generic clock source 0 1 EN1K Enable 1 kHz output 3 1 EN32K Enable 32 KHz output 2 1 FCD Flash calibration done 7 1 MODE Mode Selection 4 1 REF Reference select 5 1 TCEN Temperature Compensation Enable 1 1 RC32KIFBVERSION 32 kHz RC Oscillator Version Register 0x3F4 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 read-only VERSION Version number 0 12 read-only RC32KTUNE 32kHz RC Oscillator Tuning Register 0x28 32 read-write n 0x0 0x0 COARSE Coarse Value 16 7 FINE Fine value 0 6 UNLOCK Unlock Register 0x18 32 write-only n 0x0 0x0 ADDR Unlock Address 0 10 write-only KEY Unlock Key 24 8 write-only KEYSelect VALID Valid Key to Unlock register 0xaa VERSION BSCIF Version Register 0x3FC 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 VERSION Version Number 0 12 VREGCR Voltage Regulator Configuration Register 0x44 32 read-write n 0x0 0x0 DIS Voltage Regulator disable 0 1 SFV Store Final Value 31 1 SSG Spread Spectrum Generator Enable 8 1 SSW Stop Switching 9 1 SSWEVT Stop Switching On Event Enable 10 1 VREGIFGVERSION VREGIFA Version Register 0x3EC 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only VREGLPCSR LP Mode Control and Status Register 0x50 32 read-write n 0x0 0x0 VREGNCSR Normal Mode Control and Status Register 0x4C 32 read-write n 0x0 0x0 CATB Capacitive Touch Module B CATB 0x0 0x0 0x400 registers n CATB 75 CNTCR Counter Control Register 0x4 32 read-write n 0x0 0x0 REPEAT Repeat Measurements 28 3 SPREAD Spread Spectrum 24 4 TOP Counter Top Value 0 24 CR Control Register 0x0 32 read-write n 0x0 0x0 CHARGET Charge Time 16 4 CKSEL Clock Select 5 1 DIFF Differential Mode 6 1 DMAEN DMA Enable 7 1 EN Module Enable 0 1 ESAMPLES Number of Event Samples 8 7 ETRIG Event Triggered Operation 3 1 IIDLE Initialize Idle Value 2 1 INTRES Internal Resistors 4 1 RUN Start Operation 1 1 SWRST Software Reset 31 1 DMA Direct Memory Access Register 0x20 32 read-write n 0x0 0x0 DMA Direct Memory Access 0 32 IDLE Sensor Idle Level 0x8 32 read-write n 0x0 0x0 FIDLE Fractional Sensor Idle 0 12 RIDLE Integer Sensor Idle 12 16 IDR Interrupt Disable Register 0x2C 32 write-only n 0x0 0x0 INTCH In-touch Interrupt Disable 1 1 write-only OUTTCH Out-of-Touch Interrupt Disable 2 1 write-only SAMPLE Sample Ready Interrupt Disable 0 1 write-only IER Interrupt Enable Register 0x28 32 write-only n 0x0 0x0 INTCH In-touch Interrupt Enable 1 1 write-only OUTTCH Out-of-Touch Interrupt Enable 2 1 write-only SAMPLE Sample Ready Interrupt Enable 0 1 write-only IMR Interrupt Mask Register 0x30 32 read-only n 0x0 0x0 INTCH In-touch Interrupt Mask 1 1 read-only OUTTCH Out-of-Touch Interrupt Mask 2 1 read-only SAMPLE Sample Ready Interrupt Mask 0 1 read-only INTCH0 In-Touch Status Register 0x80 32 read-only n 0x0 0x0 INTCH In-Touch 0 32 read-only INTCH1 In-Touch Status Register 0x40 32 read-only n 0x0 0x0 INTCH In-Touch 0 32 read-only INTCHCLR0 In-Touch Status Clear Register 0xA0 32 write-only n 0x0 0x0 INTCHCLR In-Touch Clear 0 32 write-only INTCHCLR1 In-Touch Status Clear Register 0x50 32 write-only n 0x0 0x0 INTCHCLR In-Touch Clear 0 32 write-only ISR Interrupt Status Register 0x24 32 read-only n 0x0 0x0 INTCH In-touch Interrupt Status 1 1 read-only OUTTCH Out-of-Touch Interrupt Status 2 1 read-only SAMPLE Sample Ready Interrupt Status 0 1 read-only LEVEL Sensor Relative Level 0xC 32 read-only n 0x0 0x0 FLEVEL Fractional Sensor Level 0 12 read-only RLEVEL Integer Sensor Level 12 8 read-only OUTTCH0 Out-of-Touch Status Register 0xC0 32 read-only n 0x0 0x0 OUTTCH Out-of-Touch 0 32 read-only OUTTCH1 Out-of-Touch Status Register 0x60 32 read-only n 0x0 0x0 OUTTCH Out-of-Touch 0 32 read-only OUTTCHCLR0 Out-of-Touch Status Clear Register 0xE0 32 write-only n 0x0 0x0 OUTTCHCLR Out of Touch 0 32 write-only OUTTCHCLR1 Out-of-Touch Status Clear Register 0x70 32 write-only n 0x0 0x0 OUTTCHCLR Out of Touch 0 32 write-only PARAMETER Parameter Register 0xF8 32 read-only n 0x0 0x0 FRACTIONAL Number of Fractional bits 16 4 read-only NPINS Number of Pins 0 8 read-only NSTATUS Number of Status bits 8 8 read-only PINSEL Pin Selection Register 0x1C 32 read-write n 0x0 0x0 PINSEL Pin Select 0 8 RAW Sensor Raw Value 0x10 32 read-only n 0x0 0x0 RAWA Current Sensor Raw Value 16 8 read-only RAWB Last Sensor Raw Value 24 8 read-only SCR Status Clear Register 0x34 32 write-only n 0x0 0x0 INTCH In-touch 1 1 write-only OUTTCH Out-of-Touch 2 1 write-only SAMPLE Sample Ready 0 1 write-only THRESH Threshold Register 0x18 32 read-write n 0x0 0x0 DIR Threshold Direction 23 1 FTHRESH Fractional part of Threshold Value 0 12 LENGTH Threshold Length 24 5 RTHRESH Rational part of Threshold Value 12 8 TIMING Filter Timing Register 0x14 32 read-write n 0x0 0x0 TIDLE Idle Smoothening 16 12 TLEVEL Relative Level Smoothing 0 12 VERSION Version Register 0xFC 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 read-only VERSION Version number 0 12 read-only CHIPID Chip ID Registers CHIPID 0x0 0x0 0x400 registers n CIDR Chip ID Register 0x340 32 read-only n 0x0 0x0 EXID Chip ID Extension Register 0x344 32 read-only n 0x0 0x0 CRCCU CRC Calculation Unit CRCCU 0x0 0x0 0x400 registers n CRCCU 17 CR Control Register 0x34 32 write-only n 0x0 0x0 RESET Reset CRCComputation 0 1 write-only DMADIS DMA Disable Register 0xC 32 write-only n 0x0 0x0 DMADIS DMA Disable 0 1 write-only DMAEN DMA Enable Register 0x8 32 write-only n 0x0 0x0 DMAEN DMA Enable 0 1 write-only DMAIDR DMA Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 DMAIDR DMA Interrupt Disable 0 1 write-only DMAIER DMA Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 DMAIER DMA Interrupt Enable 0 1 write-only DMAIMR DMA Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 DMAIMR DMA Interrupt Mask 0 1 write-only DMAISR DMA Interrupt Status Register 0x20 32 read-only n 0x0 0x0 DMAISR DMA Interrupt Status 0 1 read-only DMASR DMA Status Register 0x10 32 read-only n 0x0 0x0 DMASR DMA Channel Status 0 1 read-only DSCR Descriptor Base Register 0x0 32 read-write n 0x0 0x0 DSCR Description Base Address 9 23 IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 ERRIDR CRC Error Interrupt Disable 0 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 ERRIER CRC Error Interrupt Enable 0 1 write-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 ERRIMR CRC Error Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 ERRISR CRC Error Interrupt Status 0 1 read-only MR Mode Register 0x38 32 read-write n 0x0 0x0 COMPARE CRC Compare 1 1 DIVIDER Bandwidth Divider 4 4 ENABLE CRC Computation Enable 0 1 PTYPE Polynomial Type 2 2 PTYPESelect CCITT8023 None 0x0 CASTAGNOLI None 0x1 CCITT16 None 0x2 SR Status Register 0x3C 32 read-only n 0x0 0x0 CRC Cyclic Redundancy Check Value 0 32 read-only VERSION Version Register 0xFC 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only DACC DAC Controller DACC 0x0 0x0 0x400 registers n DACC 70 CDR Conversion Data Register 0x8 32 write-only n 0x0 0x0 DATA Data to Convert 0 32 write-only CR Control Register 0x0 32 write-only n 0x0 0x0 SWRST Software Reset 0 1 write-only IDR Interrupt Disable Register 0x10 32 write-only n 0x0 0x0 TXRDY Transmit Ready Interrupt Disable 0 1 write-only IER Interrupt Enable Register 0xC 32 write-only n 0x0 0x0 TXRDY Transmit Ready Interrupt Enable 0 1 write-only IMR Interrupt Mask Register 0x14 32 read-only n 0x0 0x0 TXRDY Transmit Ready Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x18 32 read-only n 0x0 0x0 TXRDY Transmit Ready Interrupt Status 0 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CLKDIV Clock Divider for Internal Trigger 16 16 DACEN DAC Enable 4 1 STARTUP Startup Time Selection 8 8 TRGEN Trigger Enable 0 1 TRGSEL Trigger Selection 1 3 WORD Word Transfer 5 1 VERSION Version Register 0xFC 32 read-only n 0x0 0x0 VARIANT Variant Number 16 3 read-only VERSION Version Number 0 12 read-only WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPKEY Write Protect Key 8 24 WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPROTADDR Write Protection Error Address 8 8 read-only WPROTERR Write Protection Error 0 1 read-only EIC External Interrupt Controller EIC 0x0 0x0 0x400 registers n EIC_1 45 EIC_2 46 EIC_3 47 EIC_4 48 EIC_5 49 EIC_6 50 EIC_7 51 EIC_8 52 ASYNC Asynchronous Register 0x28 32 read-write n 0x0 0x0 INT1 External Interrupt 1 1 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 CTRL Control Register 0x38 32 read-only n 0x0 0x0 INT1 External Interrupt 1 1 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 DIS Disable Register 0x34 32 write-only n 0x0 0x0 INT1 External Interrupt 1 1 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 EDGE Edge Register 0x18 32 read-write n 0x0 0x0 INT1 External Interrupt 1 1 1 INT1Select 0 Triggers on falling edge 0x0 1 Triggers on rising edge. 0x1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT2Select 0 Triggers on falling edge 0x0 1 Triggers on rising edge. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 Triggers on falling edge 0x0 1 Triggers on rising edge. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 Triggers on falling edge 0x0 1 Triggers on rising edge. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 EN Enable Register 0x30 32 write-only n 0x0 0x0 INT1 External Interrupt 1 1 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 FILTER Filter Register 0x20 32 read-write n 0x0 0x0 INT1 External Interrupt 1 1 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 ICR Interrupt Clear Register 0x10 32 write-only n 0x0 0x0 INT1 External Interrupt 1 1 1 INT1Select 0 No effect 0x0 1 Clear Interrupt. 0x1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT2Select 0 No effect 0x0 1 Clear Interrupt. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 No effect 0x0 1 Clear Interrupt. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 No effect 0x0 1 Clear Interrupt. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 IDR Interrupt Disable Register 0x4 32 write-only n 0x0 0x0 INT1 External Interrupt 1 1 1 INT1Select 0 No effect 0x0 1 Disable Interrupt. 0x1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT2Select 0 No effect 0x0 1 Disable Interrupt. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 No effect 0x0 1 Disable Interrupt. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 No effect 0x0 1 Disable Interrupt. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 IER Interrupt Enable Register 0x0 32 write-only n 0x0 0x0 INT1 External Interrupt 1 1 1 INT1Select 0 No effect 0x0 1 Enable Interrupt. 0x1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT2Select 0 No effect 0x0 1 Enable Interrupt. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 No effect 0x0 1 Enable Interrupt. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 No effect 0x0 1 Enable Interrupt. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 IMR Interrupt Mask Register 0x8 32 read-only n 0x0 0x0 INT1 External Interrupt 1 1 1 INT1Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled. 0x1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT2Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 Interrupt is disabled 0x0 1 Interrupt is enabled. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 ISR Interrupt Status Register 0xC 32 read-only n 0x0 0x0 INT1 External Interrupt 1 1 1 INT1Select 0 An interrupt event has not occurred 0x0 1 An interrupt event has occurred. 0x1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT2Select 0 An interrupt event has not occurred 0x0 1 An interrupt event has occurred. 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 An interrupt event has not occurred 0x0 1 An interrupt event has occurred. 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 An interrupt event has not occurred 0x0 1 An interrupt event has occurred. 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 LEVEL Level Register 0x1C 32 read-write n 0x0 0x0 INT1 External Interrupt 1 1 1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT3 External Interrupt 3 3 1 INT4 External Interrupt 4 4 1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 MODE Mode Register 0x14 32 read-write n 0x0 0x0 INT1 External Interrupt 1 1 1 INT1Select 0 Edge triggered interrupt 0x0 1 Level triggered interrupt 0x1 INT10 External Interrupt 10 10 1 INT11 External Interrupt 11 11 1 INT12 External Interrupt 12 12 1 INT13 External Interrupt 13 13 1 INT14 External Interrupt 14 14 1 INT15 External Interrupt 15 15 1 INT2 External Interrupt 2 2 1 INT2Select 0 Edge triggered interrupt 0x0 1 Level triggered interrupt 0x1 INT3 External Interrupt 3 3 1 INT3Select 0 Edge triggered interrupt 0x0 1 Level triggered interrupt 0x1 INT4 External Interrupt 4 4 1 INT4Select 0 Edge triggered interrupt 0x0 1 Level triggered interrupt 0x1 INT5 External Interrupt 5 5 1 INT6 External Interrupt 6 6 1 INT7 External Interrupt 7 7 1 INT8 External Interrupt 8 8 1 INT9 External Interrupt 9 9 1 NMI External Non Maskable CPU interrupt 0 1 VERSION Version Register 0x3FC 32 read-only n 0x0 0x0 VERSION Version bits 0 12 FREQM Frequency Meter FREQM 0x0 0x0 0x400 registers n FREQM 24 CTRL Control register 0x0 32 write-only n 0x0 0x0 START Start frequency measurement 0 1 write-only ICR Interrupt Clear Register 0x20 32 write-only n 0x0 0x0 DONE Frequency measurment done 0 1 RCLKRDY Reference Clock ready 1 1 IDR Interrupt Diable Register 0x14 32 write-only n 0x0 0x0 DONE Frequency measurment done 0 1 RCLKRDY Reference Clock ready 1 1 IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DONE Frequency measurment done 0 1 write-only RCLKRDY Reference Clock ready 1 1 IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DONE Frequency measurment done 0 1 RCLKRDY Reference Clock ready 1 1 ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DONE Frequency measurment done 0 1 RCLKRDY Reference Clock ready 1 1 MODE Mode register 0x4 32 read-write n 0x0 0x0 CLKSEL Clock Source Selection 16 5 REFCEN Reference Clock Enable 31 1 REFNUM Number of Reference CLock Cycles 8 8 REFSEL Reference Clock Selection 0 2 STATUS Status register 0x8 32 read-only n 0x0 0x0 BUSY Frequency measurement on-going 0 1 RCLKBUSY Reference Clock busy 1 1 VALUE Value register 0xC 32 read-only n 0x0 0x0 VALUE Measured frequency 0 24 VERSION Version Register 0x3FC 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 GLOC Glue Logic Controller GLOC 0x0 0x0 0x400 registers n CR0 Control Register 0x0 32 read-write n 0x0 0x0 AEN Input mask 0 4 FILTEN Filter enable 31 1 CR1 Control Register 0x8 32 read-write n 0x0 0x0 AEN Input mask 0 4 FILTEN Filter enable 31 1 PARAMETER Parameter Register 0x38 32 read-only n 0x0 0x0 LUTS LUTs 0 8 TRUTH0 Truth Register 0x8 32 read-write n 0x0 0x0 TRUTH Truth 0 16 TRUTH1 Truth Register 0x14 32 read-write n 0x0 0x0 TRUTH Truth 0 16 VERSION Version Register 0x3C 32 read-only n 0x0 0x0 VARIANT Variant 16 4 VERSION Version 0 12 GPIO General-Purpose Input/Output Controller GPIO 0x0 0x0 0x1000 registers n GPIO_0 25 GPIO_1 26 GPIO_2 27 GPIO_3 28 GPIO_4 29 GPIO_5 30 GPIO_6 31 GPIO_7 32 GPIO_8 33 GPIO_9 34 GPIO_10 35 GPIO_11 36 ASR0 Access Status Register 0x3C8 32 read-write n 0x0 0x0 AR Access Error 0 1 ASR1 Access Status Register 0x7AC 32 read-write n 0x0 0x0 AR Access Error 0 1 ASR2 Access Status Register 0xD90 32 read-write n 0x0 0x0 AR Access Error 0 1 EVER0 Event Enable Register 0x300 32 read-write n 0x0 0x0 P0 Event Enable 0 1 P1 Event Enable 1 1 P10 Event Enable 10 1 P11 Event Enable 11 1 P12 Event Enable 12 1 P13 Event Enable 13 1 P14 Event Enable 14 1 P15 Event Enable 15 1 P16 Event Enable 16 1 P17 Event Enable 17 1 P18 Event Enable 18 1 P19 Event Enable 19 1 P2 Event Enable 2 1 P20 Event Enable 20 1 P21 Event Enable 21 1 P22 Event Enable 22 1 P23 Event Enable 23 1 P24 Event Enable 24 1 P25 Event Enable 25 1 P26 Event Enable 26 1 P27 Event Enable 27 1 P28 Event Enable 28 1 P29 Event Enable 29 1 P3 Event Enable 3 1 P30 Event Enable 30 1 P31 Event Enable 31 1 P4 Event Enable 4 1 P5 Event Enable 5 1 P6 Event Enable 6 1 P7 Event Enable 7 1 P8 Event Enable 8 1 P9 Event Enable 9 1 EVER1 Event Enable Register 0x680 32 read-write n 0x0 0x0 P0 Event Enable 0 1 P1 Event Enable 1 1 P10 Event Enable 10 1 P11 Event Enable 11 1 P12 Event Enable 12 1 P13 Event Enable 13 1 P14 Event Enable 14 1 P15 Event Enable 15 1 P16 Event Enable 16 1 P17 Event Enable 17 1 P18 Event Enable 18 1 P19 Event Enable 19 1 P2 Event Enable 2 1 P20 Event Enable 20 1 P21 Event Enable 21 1 P22 Event Enable 22 1 P23 Event Enable 23 1 P24 Event Enable 24 1 P25 Event Enable 25 1 P26 Event Enable 26 1 P27 Event Enable 27 1 P28 Event Enable 28 1 P29 Event Enable 29 1 P3 Event Enable 3 1 P30 Event Enable 30 1 P31 Event Enable 31 1 P4 Event Enable 4 1 P5 Event Enable 5 1 P6 Event Enable 6 1 P7 Event Enable 7 1 P8 Event Enable 8 1 P9 Event Enable 9 1 EVER2 Event Enable Register 0xC00 32 read-write n 0x0 0x0 P0 Event Enable 0 1 P1 Event Enable 1 1 P10 Event Enable 10 1 P11 Event Enable 11 1 P12 Event Enable 12 1 P13 Event Enable 13 1 P14 Event Enable 14 1 P15 Event Enable 15 1 P16 Event Enable 16 1 P17 Event Enable 17 1 P18 Event Enable 18 1 P19 Event Enable 19 1 P2 Event Enable 2 1 P20 Event Enable 20 1 P21 Event Enable 21 1 P22 Event Enable 22 1 P23 Event Enable 23 1 P24 Event Enable 24 1 P25 Event Enable 25 1 P26 Event Enable 26 1 P27 Event Enable 27 1 P28 Event Enable 28 1 P29 Event Enable 29 1 P3 Event Enable 3 1 P30 Event Enable 30 1 P31 Event Enable 31 1 P4 Event Enable 4 1 P5 Event Enable 5 1 P6 Event Enable 6 1 P7 Event Enable 7 1 P8 Event Enable 8 1 P9 Event Enable 9 1 EVERC0 Event Enable Register - Clear 0x310 32 write-only n 0x0 0x0 P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P2 Event Enable 2 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P3 Event Enable 3 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only EVERC1 Event Enable Register - Clear 0x698 32 write-only n 0x0 0x0 P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P2 Event Enable 2 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P3 Event Enable 3 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only EVERC2 Event Enable Register - Clear 0xC20 32 write-only n 0x0 0x0 P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P2 Event Enable 2 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P3 Event Enable 3 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only EVERS0 Event Enable Register - Set 0x308 32 write-only n 0x0 0x0 P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P2 Event Enable 2 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P3 Event Enable 3 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only EVERS1 Event Enable Register - Set 0x68C 32 write-only n 0x0 0x0 P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P2 Event Enable 2 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P3 Event Enable 3 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only EVERS2 Event Enable Register - Set 0xC10 32 write-only n 0x0 0x0 P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P2 Event Enable 2 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P3 Event Enable 3 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only EVERT0 Event Enable Register - Toggle 0x318 32 write-only n 0x0 0x0 P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P2 Event Enable 2 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P3 Event Enable 3 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only EVERT1 Event Enable Register - Toggle 0x6A4 32 write-only n 0x0 0x0 P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P2 Event Enable 2 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P3 Event Enable 3 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only EVERT2 Event Enable Register - Toggle 0xC30 32 write-only n 0x0 0x0 P0 Event Enable 0 1 write-only P1 Event Enable 1 1 write-only P10 Event Enable 10 1 write-only P11 Event Enable 11 1 write-only P12 Event Enable 12 1 write-only P13 Event Enable 13 1 write-only P14 Event Enable 14 1 write-only P15 Event Enable 15 1 write-only P16 Event Enable 16 1 write-only P17 Event Enable 17 1 write-only P18 Event Enable 18 1 write-only P19 Event Enable 19 1 write-only P2 Event Enable 2 1 write-only P20 Event Enable 20 1 write-only P21 Event Enable 21 1 write-only P22 Event Enable 22 1 write-only P23 Event Enable 23 1 write-only P24 Event Enable 24 1 write-only P25 Event Enable 25 1 write-only P26 Event Enable 26 1 write-only P27 Event Enable 27 1 write-only P28 Event Enable 28 1 write-only P29 Event Enable 29 1 write-only P3 Event Enable 3 1 write-only P30 Event Enable 30 1 write-only P31 Event Enable 31 1 write-only P4 Event Enable 4 1 write-only P5 Event Enable 5 1 write-only P6 Event Enable 6 1 write-only P7 Event Enable 7 1 write-only P8 Event Enable 8 1 write-only P9 Event Enable 9 1 write-only GFER0 Glitch Filter Enable Register 0x180 32 read-write n 0x0 0x0 P0 Glitch Filter Enable 0 1 P1 Glitch Filter Enable 1 1 P10 Glitch Filter Enable 10 1 P11 Glitch Filter Enable 11 1 P12 Glitch Filter Enable 12 1 P13 Glitch Filter Enable 13 1 P14 Glitch Filter Enable 14 1 P15 Glitch Filter Enable 15 1 P16 Glitch Filter Enable 16 1 P17 Glitch Filter Enable 17 1 P18 Glitch Filter Enable 18 1 P19 Glitch Filter Enable 19 1 P2 Glitch Filter Enable 2 1 P20 Glitch Filter Enable 20 1 P21 Glitch Filter Enable 21 1 P22 Glitch Filter Enable 22 1 P23 Glitch Filter Enable 23 1 P24 Glitch Filter Enable 24 1 P25 Glitch Filter Enable 25 1 P26 Glitch Filter Enable 26 1 P27 Glitch Filter Enable 27 1 P28 Glitch Filter Enable 28 1 P29 Glitch Filter Enable 29 1 P3 Glitch Filter Enable 3 1 P30 Glitch Filter Enable 30 1 P31 Glitch Filter Enable 31 1 P4 Glitch Filter Enable 4 1 P5 Glitch Filter Enable 5 1 P6 Glitch Filter Enable 6 1 P7 Glitch Filter Enable 7 1 P8 Glitch Filter Enable 8 1 P9 Glitch Filter Enable 9 1 GFER1 Glitch Filter Enable Register 0x440 32 read-write n 0x0 0x0 P0 Glitch Filter Enable 0 1 P1 Glitch Filter Enable 1 1 P10 Glitch Filter Enable 10 1 P11 Glitch Filter Enable 11 1 P12 Glitch Filter Enable 12 1 P13 Glitch Filter Enable 13 1 P14 Glitch Filter Enable 14 1 P15 Glitch Filter Enable 15 1 P16 Glitch Filter Enable 16 1 P17 Glitch Filter Enable 17 1 P18 Glitch Filter Enable 18 1 P19 Glitch Filter Enable 19 1 P2 Glitch Filter Enable 2 1 P20 Glitch Filter Enable 20 1 P21 Glitch Filter Enable 21 1 P22 Glitch Filter Enable 22 1 P23 Glitch Filter Enable 23 1 P24 Glitch Filter Enable 24 1 P25 Glitch Filter Enable 25 1 P26 Glitch Filter Enable 26 1 P27 Glitch Filter Enable 27 1 P28 Glitch Filter Enable 28 1 P29 Glitch Filter Enable 29 1 P3 Glitch Filter Enable 3 1 P30 Glitch Filter Enable 30 1 P31 Glitch Filter Enable 31 1 P4 Glitch Filter Enable 4 1 P5 Glitch Filter Enable 5 1 P6 Glitch Filter Enable 6 1 P7 Glitch Filter Enable 7 1 P8 Glitch Filter Enable 8 1 P9 Glitch Filter Enable 9 1 GFER2 Glitch Filter Enable Register 0x900 32 read-write n 0x0 0x0 P0 Glitch Filter Enable 0 1 P1 Glitch Filter Enable 1 1 P10 Glitch Filter Enable 10 1 P11 Glitch Filter Enable 11 1 P12 Glitch Filter Enable 12 1 P13 Glitch Filter Enable 13 1 P14 Glitch Filter Enable 14 1 P15 Glitch Filter Enable 15 1 P16 Glitch Filter Enable 16 1 P17 Glitch Filter Enable 17 1 P18 Glitch Filter Enable 18 1 P19 Glitch Filter Enable 19 1 P2 Glitch Filter Enable 2 1 P20 Glitch Filter Enable 20 1 P21 Glitch Filter Enable 21 1 P22 Glitch Filter Enable 22 1 P23 Glitch Filter Enable 23 1 P24 Glitch Filter Enable 24 1 P25 Glitch Filter Enable 25 1 P26 Glitch Filter Enable 26 1 P27 Glitch Filter Enable 27 1 P28 Glitch Filter Enable 28 1 P29 Glitch Filter Enable 29 1 P3 Glitch Filter Enable 3 1 P30 Glitch Filter Enable 30 1 P31 Glitch Filter Enable 31 1 P4 Glitch Filter Enable 4 1 P5 Glitch Filter Enable 5 1 P6 Glitch Filter Enable 6 1 P7 Glitch Filter Enable 7 1 P8 Glitch Filter Enable 8 1 P9 Glitch Filter Enable 9 1 GFERC0 Glitch Filter Enable Register - Clear 0x190 32 write-only n 0x0 0x0 P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P2 Glitch Filter Enable 2 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P3 Glitch Filter Enable 3 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only GFERC1 Glitch Filter Enable Register - Clear 0x458 32 write-only n 0x0 0x0 P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P2 Glitch Filter Enable 2 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P3 Glitch Filter Enable 3 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only GFERC2 Glitch Filter Enable Register - Clear 0x920 32 write-only n 0x0 0x0 P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P2 Glitch Filter Enable 2 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P3 Glitch Filter Enable 3 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only GFERS0 Glitch Filter Enable Register - Set 0x188 32 write-only n 0x0 0x0 P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P2 Glitch Filter Enable 2 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P3 Glitch Filter Enable 3 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only GFERS1 Glitch Filter Enable Register - Set 0x44C 32 write-only n 0x0 0x0 P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P2 Glitch Filter Enable 2 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P3 Glitch Filter Enable 3 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only GFERS2 Glitch Filter Enable Register - Set 0x910 32 write-only n 0x0 0x0 P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P2 Glitch Filter Enable 2 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P3 Glitch Filter Enable 3 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only GFERT0 Glitch Filter Enable Register - Toggle 0x198 32 write-only n 0x0 0x0 P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P2 Glitch Filter Enable 2 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P3 Glitch Filter Enable 3 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only GFERT1 Glitch Filter Enable Register - Toggle 0x464 32 write-only n 0x0 0x0 P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P2 Glitch Filter Enable 2 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P3 Glitch Filter Enable 3 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only GFERT2 Glitch Filter Enable Register - Toggle 0x930 32 write-only n 0x0 0x0 P0 Glitch Filter Enable 0 1 write-only P1 Glitch Filter Enable 1 1 write-only P10 Glitch Filter Enable 10 1 write-only P11 Glitch Filter Enable 11 1 write-only P12 Glitch Filter Enable 12 1 write-only P13 Glitch Filter Enable 13 1 write-only P14 Glitch Filter Enable 14 1 write-only P15 Glitch Filter Enable 15 1 write-only P16 Glitch Filter Enable 16 1 write-only P17 Glitch Filter Enable 17 1 write-only P18 Glitch Filter Enable 18 1 write-only P19 Glitch Filter Enable 19 1 write-only P2 Glitch Filter Enable 2 1 write-only P20 Glitch Filter Enable 20 1 write-only P21 Glitch Filter Enable 21 1 write-only P22 Glitch Filter Enable 22 1 write-only P23 Glitch Filter Enable 23 1 write-only P24 Glitch Filter Enable 24 1 write-only P25 Glitch Filter Enable 25 1 write-only P26 Glitch Filter Enable 26 1 write-only P27 Glitch Filter Enable 27 1 write-only P28 Glitch Filter Enable 28 1 write-only P29 Glitch Filter Enable 29 1 write-only P3 Glitch Filter Enable 3 1 write-only P30 Glitch Filter Enable 30 1 write-only P31 Glitch Filter Enable 31 1 write-only P4 Glitch Filter Enable 4 1 write-only P5 Glitch Filter Enable 5 1 write-only P6 Glitch Filter Enable 6 1 write-only P7 Glitch Filter Enable 7 1 write-only P8 Glitch Filter Enable 8 1 write-only P9 Glitch Filter Enable 9 1 write-only GPER0 GPIO Enable Register 0x0 32 read-write n 0x0 0x0 P0 GPIO Enable 0 1 P1 GPIO Enable 1 1 P10 GPIO Enable 10 1 P11 GPIO Enable 11 1 P12 GPIO Enable 12 1 P13 GPIO Enable 13 1 P14 GPIO Enable 14 1 P15 GPIO Enable 15 1 P16 GPIO Enable 16 1 P17 GPIO Enable 17 1 P18 GPIO Enable 18 1 P19 GPIO Enable 19 1 P2 GPIO Enable 2 1 P20 GPIO Enable 20 1 P21 GPIO Enable 21 1 P22 GPIO Enable 22 1 P23 GPIO Enable 23 1 P24 GPIO Enable 24 1 P25 GPIO Enable 25 1 P26 GPIO Enable 26 1 P27 GPIO Enable 27 1 P28 GPIO Enable 28 1 P29 GPIO Enable 29 1 P3 GPIO Enable 3 1 P30 GPIO Enable 30 1 P31 GPIO Enable 31 1 P4 GPIO Enable 4 1 P5 GPIO Enable 5 1 P6 GPIO Enable 6 1 P7 GPIO Enable 7 1 P8 GPIO Enable 8 1 P9 GPIO Enable 9 1 GPER1 GPIO Enable Register 0x200 32 read-write n 0x0 0x0 P0 GPIO Enable 0 1 P1 GPIO Enable 1 1 P10 GPIO Enable 10 1 P11 GPIO Enable 11 1 P12 GPIO Enable 12 1 P13 GPIO Enable 13 1 P14 GPIO Enable 14 1 P15 GPIO Enable 15 1 P16 GPIO Enable 16 1 P17 GPIO Enable 17 1 P18 GPIO Enable 18 1 P19 GPIO Enable 19 1 P2 GPIO Enable 2 1 P20 GPIO Enable 20 1 P21 GPIO Enable 21 1 P22 GPIO Enable 22 1 P23 GPIO Enable 23 1 P24 GPIO Enable 24 1 P25 GPIO Enable 25 1 P26 GPIO Enable 26 1 P27 GPIO Enable 27 1 P28 GPIO Enable 28 1 P29 GPIO Enable 29 1 P3 GPIO Enable 3 1 P30 GPIO Enable 30 1 P31 GPIO Enable 31 1 P4 GPIO Enable 4 1 P5 GPIO Enable 5 1 P6 GPIO Enable 6 1 P7 GPIO Enable 7 1 P8 GPIO Enable 8 1 P9 GPIO Enable 9 1 GPER2 GPIO Enable Register 0x600 32 read-write n 0x0 0x0 P0 GPIO Enable 0 1 P1 GPIO Enable 1 1 P10 GPIO Enable 10 1 P11 GPIO Enable 11 1 P12 GPIO Enable 12 1 P13 GPIO Enable 13 1 P14 GPIO Enable 14 1 P15 GPIO Enable 15 1 P16 GPIO Enable 16 1 P17 GPIO Enable 17 1 P18 GPIO Enable 18 1 P19 GPIO Enable 19 1 P2 GPIO Enable 2 1 P20 GPIO Enable 20 1 P21 GPIO Enable 21 1 P22 GPIO Enable 22 1 P23 GPIO Enable 23 1 P24 GPIO Enable 24 1 P25 GPIO Enable 25 1 P26 GPIO Enable 26 1 P27 GPIO Enable 27 1 P28 GPIO Enable 28 1 P29 GPIO Enable 29 1 P3 GPIO Enable 3 1 P30 GPIO Enable 30 1 P31 GPIO Enable 31 1 P4 GPIO Enable 4 1 P5 GPIO Enable 5 1 P6 GPIO Enable 6 1 P7 GPIO Enable 7 1 P8 GPIO Enable 8 1 P9 GPIO Enable 9 1 GPERC0 GPIO Enable Register - Clear 0x10 32 write-only n 0x0 0x0 P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P2 GPIO Enable 2 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P3 GPIO Enable 3 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only GPERC1 GPIO Enable Register - Clear 0x218 32 write-only n 0x0 0x0 P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P2 GPIO Enable 2 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P3 GPIO Enable 3 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only GPERC2 GPIO Enable Register - Clear 0x620 32 write-only n 0x0 0x0 P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P2 GPIO Enable 2 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P3 GPIO Enable 3 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only GPERS0 GPIO Enable Register - Set 0x8 32 write-only n 0x0 0x0 P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P2 GPIO Enable 2 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P3 GPIO Enable 3 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only GPERS1 GPIO Enable Register - Set 0x20C 32 write-only n 0x0 0x0 P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P2 GPIO Enable 2 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P3 GPIO Enable 3 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only GPERS2 GPIO Enable Register - Set 0x610 32 write-only n 0x0 0x0 P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P2 GPIO Enable 2 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P3 GPIO Enable 3 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only GPERT0 GPIO Enable Register - Toggle 0x18 32 write-only n 0x0 0x0 P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P2 GPIO Enable 2 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P3 GPIO Enable 3 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only GPERT1 GPIO Enable Register - Toggle 0x224 32 write-only n 0x0 0x0 P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P2 GPIO Enable 2 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P3 GPIO Enable 3 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only GPERT2 GPIO Enable Register - Toggle 0x630 32 write-only n 0x0 0x0 P0 GPIO Enable 0 1 write-only P1 GPIO Enable 1 1 write-only P10 GPIO Enable 10 1 write-only P11 GPIO Enable 11 1 write-only P12 GPIO Enable 12 1 write-only P13 GPIO Enable 13 1 write-only P14 GPIO Enable 14 1 write-only P15 GPIO Enable 15 1 write-only P16 GPIO Enable 16 1 write-only P17 GPIO Enable 17 1 write-only P18 GPIO Enable 18 1 write-only P19 GPIO Enable 19 1 write-only P2 GPIO Enable 2 1 write-only P20 GPIO Enable 20 1 write-only P21 GPIO Enable 21 1 write-only P22 GPIO Enable 22 1 write-only P23 GPIO Enable 23 1 write-only P24 GPIO Enable 24 1 write-only P25 GPIO Enable 25 1 write-only P26 GPIO Enable 26 1 write-only P27 GPIO Enable 27 1 write-only P28 GPIO Enable 28 1 write-only P29 GPIO Enable 29 1 write-only P3 GPIO Enable 3 1 write-only P30 GPIO Enable 30 1 write-only P31 GPIO Enable 31 1 write-only P4 GPIO Enable 4 1 write-only P5 GPIO Enable 5 1 write-only P6 GPIO Enable 6 1 write-only P7 GPIO Enable 7 1 write-only P8 GPIO Enable 8 1 write-only P9 GPIO Enable 9 1 write-only IER0 Interrupt Enable Register 0x120 32 read-write n 0x0 0x0 P0 Interrupt Enable 0 1 P1 Interrupt Enable 1 1 P10 Interrupt Enable 10 1 P11 Interrupt Enable 11 1 P12 Interrupt Enable 12 1 P13 Interrupt Enable 13 1 P14 Interrupt Enable 14 1 P15 Interrupt Enable 15 1 P16 Interrupt Enable 16 1 P17 Interrupt Enable 17 1 P18 Interrupt Enable 18 1 P19 Interrupt Enable 19 1 P2 Interrupt Enable 2 1 P20 Interrupt Enable 20 1 P21 Interrupt Enable 21 1 P22 Interrupt Enable 22 1 P23 Interrupt Enable 23 1 P24 Interrupt Enable 24 1 P25 Interrupt Enable 25 1 P26 Interrupt Enable 26 1 P27 Interrupt Enable 27 1 P28 Interrupt Enable 28 1 P29 Interrupt Enable 29 1 P3 Interrupt Enable 3 1 P30 Interrupt Enable 30 1 P31 Interrupt Enable 31 1 P4 Interrupt Enable 4 1 P5 Interrupt Enable 5 1 P6 Interrupt Enable 6 1 P7 Interrupt Enable 7 1 P8 Interrupt Enable 8 1 P9 Interrupt Enable 9 1 IER1 Interrupt Enable Register 0x3B0 32 read-write n 0x0 0x0 P0 Interrupt Enable 0 1 P1 Interrupt Enable 1 1 P10 Interrupt Enable 10 1 P11 Interrupt Enable 11 1 P12 Interrupt Enable 12 1 P13 Interrupt Enable 13 1 P14 Interrupt Enable 14 1 P15 Interrupt Enable 15 1 P16 Interrupt Enable 16 1 P17 Interrupt Enable 17 1 P18 Interrupt Enable 18 1 P19 Interrupt Enable 19 1 P2 Interrupt Enable 2 1 P20 Interrupt Enable 20 1 P21 Interrupt Enable 21 1 P22 Interrupt Enable 22 1 P23 Interrupt Enable 23 1 P24 Interrupt Enable 24 1 P25 Interrupt Enable 25 1 P26 Interrupt Enable 26 1 P27 Interrupt Enable 27 1 P28 Interrupt Enable 28 1 P29 Interrupt Enable 29 1 P3 Interrupt Enable 3 1 P30 Interrupt Enable 30 1 P31 Interrupt Enable 31 1 P4 Interrupt Enable 4 1 P5 Interrupt Enable 5 1 P6 Interrupt Enable 6 1 P7 Interrupt Enable 7 1 P8 Interrupt Enable 8 1 P9 Interrupt Enable 9 1 IER2 Interrupt Enable Register 0x840 32 read-write n 0x0 0x0 P0 Interrupt Enable 0 1 P1 Interrupt Enable 1 1 P10 Interrupt Enable 10 1 P11 Interrupt Enable 11 1 P12 Interrupt Enable 12 1 P13 Interrupt Enable 13 1 P14 Interrupt Enable 14 1 P15 Interrupt Enable 15 1 P16 Interrupt Enable 16 1 P17 Interrupt Enable 17 1 P18 Interrupt Enable 18 1 P19 Interrupt Enable 19 1 P2 Interrupt Enable 2 1 P20 Interrupt Enable 20 1 P21 Interrupt Enable 21 1 P22 Interrupt Enable 22 1 P23 Interrupt Enable 23 1 P24 Interrupt Enable 24 1 P25 Interrupt Enable 25 1 P26 Interrupt Enable 26 1 P27 Interrupt Enable 27 1 P28 Interrupt Enable 28 1 P29 Interrupt Enable 29 1 P3 Interrupt Enable 3 1 P30 Interrupt Enable 30 1 P31 Interrupt Enable 31 1 P4 Interrupt Enable 4 1 P5 Interrupt Enable 5 1 P6 Interrupt Enable 6 1 P7 Interrupt Enable 7 1 P8 Interrupt Enable 8 1 P9 Interrupt Enable 9 1 IERC0 Interrupt Enable Register - Clear 0x130 32 write-only n 0x0 0x0 P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P2 Interrupt Enable 2 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P3 Interrupt Enable 3 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only IERC1 Interrupt Enable Register - Clear 0x3C8 32 write-only n 0x0 0x0 P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P2 Interrupt Enable 2 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P3 Interrupt Enable 3 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only IERC2 Interrupt Enable Register - Clear 0x860 32 write-only n 0x0 0x0 P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P2 Interrupt Enable 2 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P3 Interrupt Enable 3 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only IERS0 Interrupt Enable Register - Set 0x128 32 write-only n 0x0 0x0 P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P2 Interrupt Enable 2 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P3 Interrupt Enable 3 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only IERS1 Interrupt Enable Register - Set 0x3BC 32 write-only n 0x0 0x0 P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P2 Interrupt Enable 2 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P3 Interrupt Enable 3 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only IERS2 Interrupt Enable Register - Set 0x850 32 write-only n 0x0 0x0 P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P2 Interrupt Enable 2 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P3 Interrupt Enable 3 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only IERT0 Interrupt Enable Register - Toggle 0x138 32 write-only n 0x0 0x0 P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P2 Interrupt Enable 2 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P3 Interrupt Enable 3 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only IERT1 Interrupt Enable Register - Toggle 0x3D4 32 write-only n 0x0 0x0 P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P2 Interrupt Enable 2 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P3 Interrupt Enable 3 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only IERT2 Interrupt Enable Register - Toggle 0x870 32 write-only n 0x0 0x0 P0 Interrupt Enable 0 1 write-only P1 Interrupt Enable 1 1 write-only P10 Interrupt Enable 10 1 write-only P11 Interrupt Enable 11 1 write-only P12 Interrupt Enable 12 1 write-only P13 Interrupt Enable 13 1 write-only P14 Interrupt Enable 14 1 write-only P15 Interrupt Enable 15 1 write-only P16 Interrupt Enable 16 1 write-only P17 Interrupt Enable 17 1 write-only P18 Interrupt Enable 18 1 write-only P19 Interrupt Enable 19 1 write-only P2 Interrupt Enable 2 1 write-only P20 Interrupt Enable 20 1 write-only P21 Interrupt Enable 21 1 write-only P22 Interrupt Enable 22 1 write-only P23 Interrupt Enable 23 1 write-only P24 Interrupt Enable 24 1 write-only P25 Interrupt Enable 25 1 write-only P26 Interrupt Enable 26 1 write-only P27 Interrupt Enable 27 1 write-only P28 Interrupt Enable 28 1 write-only P29 Interrupt Enable 29 1 write-only P3 Interrupt Enable 3 1 write-only P30 Interrupt Enable 30 1 write-only P31 Interrupt Enable 31 1 write-only P4 Interrupt Enable 4 1 write-only P5 Interrupt Enable 5 1 write-only P6 Interrupt Enable 6 1 write-only P7 Interrupt Enable 7 1 write-only P8 Interrupt Enable 8 1 write-only P9 Interrupt Enable 9 1 write-only IFR0 Interrupt Flag Register 0x1A0 32 read-only n 0x0 0x0 P0 Interrupt Flag 0 1 read-only P1 Interrupt Flag 1 1 read-only P10 Interrupt Flag 10 1 read-only P11 Interrupt Flag 11 1 read-only P12 Interrupt Flag 12 1 read-only P13 Interrupt Flag 13 1 read-only P14 Interrupt Flag 14 1 read-only P15 Interrupt Flag 15 1 read-only P16 Interrupt Flag 16 1 read-only P17 Interrupt Flag 17 1 read-only P18 Interrupt Flag 18 1 read-only P19 Interrupt Flag 19 1 read-only P2 Interrupt Flag 2 1 read-only P20 Interrupt Flag 20 1 read-only P21 Interrupt Flag 21 1 read-only P22 Interrupt Flag 22 1 read-only P23 Interrupt Flag 23 1 read-only P24 Interrupt Flag 24 1 read-only P25 Interrupt Flag 25 1 read-only P26 Interrupt Flag 26 1 read-only P27 Interrupt Flag 27 1 read-only P28 Interrupt Flag 28 1 read-only P29 Interrupt Flag 29 1 read-only P3 Interrupt Flag 3 1 read-only P30 Interrupt Flag 30 1 read-only P31 Interrupt Flag 31 1 read-only P4 Interrupt Flag 4 1 read-only P5 Interrupt Flag 5 1 read-only P6 Interrupt Flag 6 1 read-only P7 Interrupt Flag 7 1 read-only P8 Interrupt Flag 8 1 read-only P9 Interrupt Flag 9 1 read-only IFR1 Interrupt Flag Register 0x470 32 read-only n 0x0 0x0 P0 Interrupt Flag 0 1 read-only P1 Interrupt Flag 1 1 read-only P10 Interrupt Flag 10 1 read-only P11 Interrupt Flag 11 1 read-only P12 Interrupt Flag 12 1 read-only P13 Interrupt Flag 13 1 read-only P14 Interrupt Flag 14 1 read-only P15 Interrupt Flag 15 1 read-only P16 Interrupt Flag 16 1 read-only P17 Interrupt Flag 17 1 read-only P18 Interrupt Flag 18 1 read-only P19 Interrupt Flag 19 1 read-only P2 Interrupt Flag 2 1 read-only P20 Interrupt Flag 20 1 read-only P21 Interrupt Flag 21 1 read-only P22 Interrupt Flag 22 1 read-only P23 Interrupt Flag 23 1 read-only P24 Interrupt Flag 24 1 read-only P25 Interrupt Flag 25 1 read-only P26 Interrupt Flag 26 1 read-only P27 Interrupt Flag 27 1 read-only P28 Interrupt Flag 28 1 read-only P29 Interrupt Flag 29 1 read-only P3 Interrupt Flag 3 1 read-only P30 Interrupt Flag 30 1 read-only P31 Interrupt Flag 31 1 read-only P4 Interrupt Flag 4 1 read-only P5 Interrupt Flag 5 1 read-only P6 Interrupt Flag 6 1 read-only P7 Interrupt Flag 7 1 read-only P8 Interrupt Flag 8 1 read-only P9 Interrupt Flag 9 1 read-only IFR2 Interrupt Flag Register 0x940 32 read-only n 0x0 0x0 P0 Interrupt Flag 0 1 read-only P1 Interrupt Flag 1 1 read-only P10 Interrupt Flag 10 1 read-only P11 Interrupt Flag 11 1 read-only P12 Interrupt Flag 12 1 read-only P13 Interrupt Flag 13 1 read-only P14 Interrupt Flag 14 1 read-only P15 Interrupt Flag 15 1 read-only P16 Interrupt Flag 16 1 read-only P17 Interrupt Flag 17 1 read-only P18 Interrupt Flag 18 1 read-only P19 Interrupt Flag 19 1 read-only P2 Interrupt Flag 2 1 read-only P20 Interrupt Flag 20 1 read-only P21 Interrupt Flag 21 1 read-only P22 Interrupt Flag 22 1 read-only P23 Interrupt Flag 23 1 read-only P24 Interrupt Flag 24 1 read-only P25 Interrupt Flag 25 1 read-only P26 Interrupt Flag 26 1 read-only P27 Interrupt Flag 27 1 read-only P28 Interrupt Flag 28 1 read-only P29 Interrupt Flag 29 1 read-only P3 Interrupt Flag 3 1 read-only P30 Interrupt Flag 30 1 read-only P31 Interrupt Flag 31 1 read-only P4 Interrupt Flag 4 1 read-only P5 Interrupt Flag 5 1 read-only P6 Interrupt Flag 6 1 read-only P7 Interrupt Flag 7 1 read-only P8 Interrupt Flag 8 1 read-only P9 Interrupt Flag 9 1 read-only IFRC0 Interrupt Flag Register - Clear 0x1B0 32 write-only n 0x0 0x0 P0 Interrupt Flag 0 1 write-only P1 Interrupt Flag 1 1 write-only P10 Interrupt Flag 10 1 write-only P11 Interrupt Flag 11 1 write-only P12 Interrupt Flag 12 1 write-only P13 Interrupt Flag 13 1 write-only P14 Interrupt Flag 14 1 write-only P15 Interrupt Flag 15 1 write-only P16 Interrupt Flag 16 1 write-only P17 Interrupt Flag 17 1 write-only P18 Interrupt Flag 18 1 write-only P19 Interrupt Flag 19 1 write-only P2 Interrupt Flag 2 1 write-only P20 Interrupt Flag 20 1 write-only P21 Interrupt Flag 21 1 write-only P22 Interrupt Flag 22 1 write-only P23 Interrupt Flag 23 1 write-only P24 Interrupt Flag 24 1 write-only P25 Interrupt Flag 25 1 write-only P26 Interrupt Flag 26 1 write-only P27 Interrupt Flag 27 1 write-only P28 Interrupt Flag 28 1 write-only P29 Interrupt Flag 29 1 write-only P3 Interrupt Flag 3 1 write-only P30 Interrupt Flag 30 1 write-only P31 Interrupt Flag 31 1 write-only P4 Interrupt Flag 4 1 write-only P5 Interrupt Flag 5 1 write-only P6 Interrupt Flag 6 1 write-only P7 Interrupt Flag 7 1 write-only P8 Interrupt Flag 8 1 write-only P9 Interrupt Flag 9 1 write-only IFRC1 Interrupt Flag Register - Clear 0x488 32 write-only n 0x0 0x0 P0 Interrupt Flag 0 1 write-only P1 Interrupt Flag 1 1 write-only P10 Interrupt Flag 10 1 write-only P11 Interrupt Flag 11 1 write-only P12 Interrupt Flag 12 1 write-only P13 Interrupt Flag 13 1 write-only P14 Interrupt Flag 14 1 write-only P15 Interrupt Flag 15 1 write-only P16 Interrupt Flag 16 1 write-only P17 Interrupt Flag 17 1 write-only P18 Interrupt Flag 18 1 write-only P19 Interrupt Flag 19 1 write-only P2 Interrupt Flag 2 1 write-only P20 Interrupt Flag 20 1 write-only P21 Interrupt Flag 21 1 write-only P22 Interrupt Flag 22 1 write-only P23 Interrupt Flag 23 1 write-only P24 Interrupt Flag 24 1 write-only P25 Interrupt Flag 25 1 write-only P26 Interrupt Flag 26 1 write-only P27 Interrupt Flag 27 1 write-only P28 Interrupt Flag 28 1 write-only P29 Interrupt Flag 29 1 write-only P3 Interrupt Flag 3 1 write-only P30 Interrupt Flag 30 1 write-only P31 Interrupt Flag 31 1 write-only P4 Interrupt Flag 4 1 write-only P5 Interrupt Flag 5 1 write-only P6 Interrupt Flag 6 1 write-only P7 Interrupt Flag 7 1 write-only P8 Interrupt Flag 8 1 write-only P9 Interrupt Flag 9 1 write-only IFRC2 Interrupt Flag Register - Clear 0x960 32 write-only n 0x0 0x0 P0 Interrupt Flag 0 1 write-only P1 Interrupt Flag 1 1 write-only P10 Interrupt Flag 10 1 write-only P11 Interrupt Flag 11 1 write-only P12 Interrupt Flag 12 1 write-only P13 Interrupt Flag 13 1 write-only P14 Interrupt Flag 14 1 write-only P15 Interrupt Flag 15 1 write-only P16 Interrupt Flag 16 1 write-only P17 Interrupt Flag 17 1 write-only P18 Interrupt Flag 18 1 write-only P19 Interrupt Flag 19 1 write-only P2 Interrupt Flag 2 1 write-only P20 Interrupt Flag 20 1 write-only P21 Interrupt Flag 21 1 write-only P22 Interrupt Flag 22 1 write-only P23 Interrupt Flag 23 1 write-only P24 Interrupt Flag 24 1 write-only P25 Interrupt Flag 25 1 write-only P26 Interrupt Flag 26 1 write-only P27 Interrupt Flag 27 1 write-only P28 Interrupt Flag 28 1 write-only P29 Interrupt Flag 29 1 write-only P3 Interrupt Flag 3 1 write-only P30 Interrupt Flag 30 1 write-only P31 Interrupt Flag 31 1 write-only P4 Interrupt Flag 4 1 write-only P5 Interrupt Flag 5 1 write-only P6 Interrupt Flag 6 1 write-only P7 Interrupt Flag 7 1 write-only P8 Interrupt Flag 8 1 write-only P9 Interrupt Flag 9 1 write-only IMR00 Interrupt Mode Register 0 0x140 32 read-write n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 P1 Interrupt Mode Bit 0 1 1 P10 Interrupt Mode Bit 0 10 1 P11 Interrupt Mode Bit 0 11 1 P12 Interrupt Mode Bit 0 12 1 P13 Interrupt Mode Bit 0 13 1 P14 Interrupt Mode Bit 0 14 1 P15 Interrupt Mode Bit 0 15 1 P16 Interrupt Mode Bit 0 16 1 P17 Interrupt Mode Bit 0 17 1 P18 Interrupt Mode Bit 0 18 1 P19 Interrupt Mode Bit 0 19 1 P2 Interrupt Mode Bit 0 2 1 P20 Interrupt Mode Bit 0 20 1 P21 Interrupt Mode Bit 0 21 1 P22 Interrupt Mode Bit 0 22 1 P23 Interrupt Mode Bit 0 23 1 P24 Interrupt Mode Bit 0 24 1 P25 Interrupt Mode Bit 0 25 1 P26 Interrupt Mode Bit 0 26 1 P27 Interrupt Mode Bit 0 27 1 P28 Interrupt Mode Bit 0 28 1 P29 Interrupt Mode Bit 0 29 1 P3 Interrupt Mode Bit 0 3 1 P30 Interrupt Mode Bit 0 30 1 P31 Interrupt Mode Bit 0 31 1 P4 Interrupt Mode Bit 0 4 1 P5 Interrupt Mode Bit 0 5 1 P6 Interrupt Mode Bit 0 6 1 P7 Interrupt Mode Bit 0 7 1 P8 Interrupt Mode Bit 0 8 1 P9 Interrupt Mode Bit 0 9 1 IMR01 Interrupt Mode Register 0 0x3E0 32 read-write n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 P1 Interrupt Mode Bit 0 1 1 P10 Interrupt Mode Bit 0 10 1 P11 Interrupt Mode Bit 0 11 1 P12 Interrupt Mode Bit 0 12 1 P13 Interrupt Mode Bit 0 13 1 P14 Interrupt Mode Bit 0 14 1 P15 Interrupt Mode Bit 0 15 1 P16 Interrupt Mode Bit 0 16 1 P17 Interrupt Mode Bit 0 17 1 P18 Interrupt Mode Bit 0 18 1 P19 Interrupt Mode Bit 0 19 1 P2 Interrupt Mode Bit 0 2 1 P20 Interrupt Mode Bit 0 20 1 P21 Interrupt Mode Bit 0 21 1 P22 Interrupt Mode Bit 0 22 1 P23 Interrupt Mode Bit 0 23 1 P24 Interrupt Mode Bit 0 24 1 P25 Interrupt Mode Bit 0 25 1 P26 Interrupt Mode Bit 0 26 1 P27 Interrupt Mode Bit 0 27 1 P28 Interrupt Mode Bit 0 28 1 P29 Interrupt Mode Bit 0 29 1 P3 Interrupt Mode Bit 0 3 1 P30 Interrupt Mode Bit 0 30 1 P31 Interrupt Mode Bit 0 31 1 P4 Interrupt Mode Bit 0 4 1 P5 Interrupt Mode Bit 0 5 1 P6 Interrupt Mode Bit 0 6 1 P7 Interrupt Mode Bit 0 7 1 P8 Interrupt Mode Bit 0 8 1 P9 Interrupt Mode Bit 0 9 1 IMR02 Interrupt Mode Register 0 0x880 32 read-write n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 P1 Interrupt Mode Bit 0 1 1 P10 Interrupt Mode Bit 0 10 1 P11 Interrupt Mode Bit 0 11 1 P12 Interrupt Mode Bit 0 12 1 P13 Interrupt Mode Bit 0 13 1 P14 Interrupt Mode Bit 0 14 1 P15 Interrupt Mode Bit 0 15 1 P16 Interrupt Mode Bit 0 16 1 P17 Interrupt Mode Bit 0 17 1 P18 Interrupt Mode Bit 0 18 1 P19 Interrupt Mode Bit 0 19 1 P2 Interrupt Mode Bit 0 2 1 P20 Interrupt Mode Bit 0 20 1 P21 Interrupt Mode Bit 0 21 1 P22 Interrupt Mode Bit 0 22 1 P23 Interrupt Mode Bit 0 23 1 P24 Interrupt Mode Bit 0 24 1 P25 Interrupt Mode Bit 0 25 1 P26 Interrupt Mode Bit 0 26 1 P27 Interrupt Mode Bit 0 27 1 P28 Interrupt Mode Bit 0 28 1 P29 Interrupt Mode Bit 0 29 1 P3 Interrupt Mode Bit 0 3 1 P30 Interrupt Mode Bit 0 30 1 P31 Interrupt Mode Bit 0 31 1 P4 Interrupt Mode Bit 0 4 1 P5 Interrupt Mode Bit 0 5 1 P6 Interrupt Mode Bit 0 6 1 P7 Interrupt Mode Bit 0 7 1 P8 Interrupt Mode Bit 0 8 1 P9 Interrupt Mode Bit 0 9 1 IMR0C0 Interrupt Mode Register 0 - Clear 0x150 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only IMR0C1 Interrupt Mode Register 0 - Clear 0x3F8 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only IMR0C2 Interrupt Mode Register 0 - Clear 0x8A0 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only IMR0S0 Interrupt Mode Register 0 - Set 0x148 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only IMR0S1 Interrupt Mode Register 0 - Set 0x3EC 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only IMR0S2 Interrupt Mode Register 0 - Set 0x890 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only IMR0T0 Interrupt Mode Register 0 - Toggle 0x158 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only IMR0T1 Interrupt Mode Register 0 - Toggle 0x404 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only IMR0T2 Interrupt Mode Register 0 - Toggle 0x8B0 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 0 0 1 write-only P1 Interrupt Mode Bit 0 1 1 write-only P10 Interrupt Mode Bit 0 10 1 write-only P11 Interrupt Mode Bit 0 11 1 write-only P12 Interrupt Mode Bit 0 12 1 write-only P13 Interrupt Mode Bit 0 13 1 write-only P14 Interrupt Mode Bit 0 14 1 write-only P15 Interrupt Mode Bit 0 15 1 write-only P16 Interrupt Mode Bit 0 16 1 write-only P17 Interrupt Mode Bit 0 17 1 write-only P18 Interrupt Mode Bit 0 18 1 write-only P19 Interrupt Mode Bit 0 19 1 write-only P2 Interrupt Mode Bit 0 2 1 write-only P20 Interrupt Mode Bit 0 20 1 write-only P21 Interrupt Mode Bit 0 21 1 write-only P22 Interrupt Mode Bit 0 22 1 write-only P23 Interrupt Mode Bit 0 23 1 write-only P24 Interrupt Mode Bit 0 24 1 write-only P25 Interrupt Mode Bit 0 25 1 write-only P26 Interrupt Mode Bit 0 26 1 write-only P27 Interrupt Mode Bit 0 27 1 write-only P28 Interrupt Mode Bit 0 28 1 write-only P29 Interrupt Mode Bit 0 29 1 write-only P3 Interrupt Mode Bit 0 3 1 write-only P30 Interrupt Mode Bit 0 30 1 write-only P31 Interrupt Mode Bit 0 31 1 write-only P4 Interrupt Mode Bit 0 4 1 write-only P5 Interrupt Mode Bit 0 5 1 write-only P6 Interrupt Mode Bit 0 6 1 write-only P7 Interrupt Mode Bit 0 7 1 write-only P8 Interrupt Mode Bit 0 8 1 write-only P9 Interrupt Mode Bit 0 9 1 write-only IMR10 Interrupt Mode Register 1 0x160 32 read-write n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 P1 Interrupt Mode Bit 1 1 1 P10 Interrupt Mode Bit 1 10 1 P11 Interrupt Mode Bit 1 11 1 P12 Interrupt Mode Bit 1 12 1 P13 Interrupt Mode Bit 1 13 1 P14 Interrupt Mode Bit 1 14 1 P15 Interrupt Mode Bit 1 15 1 P16 Interrupt Mode Bit 1 16 1 P17 Interrupt Mode Bit 1 17 1 P18 Interrupt Mode Bit 1 18 1 P19 Interrupt Mode Bit 1 19 1 P2 Interrupt Mode Bit 1 2 1 P20 Interrupt Mode Bit 1 20 1 P21 Interrupt Mode Bit 1 21 1 P22 Interrupt Mode Bit 1 22 1 P23 Interrupt Mode Bit 1 23 1 P24 Interrupt Mode Bit 1 24 1 P25 Interrupt Mode Bit 1 25 1 P26 Interrupt Mode Bit 1 26 1 P27 Interrupt Mode Bit 1 27 1 P28 Interrupt Mode Bit 1 28 1 P29 Interrupt Mode Bit 1 29 1 P3 Interrupt Mode Bit 1 3 1 P30 Interrupt Mode Bit 1 30 1 P31 Interrupt Mode Bit 1 31 1 P4 Interrupt Mode Bit 1 4 1 P5 Interrupt Mode Bit 1 5 1 P6 Interrupt Mode Bit 1 6 1 P7 Interrupt Mode Bit 1 7 1 P8 Interrupt Mode Bit 1 8 1 P9 Interrupt Mode Bit 1 9 1 IMR11 Interrupt Mode Register 1 0x410 32 read-write n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 P1 Interrupt Mode Bit 1 1 1 P10 Interrupt Mode Bit 1 10 1 P11 Interrupt Mode Bit 1 11 1 P12 Interrupt Mode Bit 1 12 1 P13 Interrupt Mode Bit 1 13 1 P14 Interrupt Mode Bit 1 14 1 P15 Interrupt Mode Bit 1 15 1 P16 Interrupt Mode Bit 1 16 1 P17 Interrupt Mode Bit 1 17 1 P18 Interrupt Mode Bit 1 18 1 P19 Interrupt Mode Bit 1 19 1 P2 Interrupt Mode Bit 1 2 1 P20 Interrupt Mode Bit 1 20 1 P21 Interrupt Mode Bit 1 21 1 P22 Interrupt Mode Bit 1 22 1 P23 Interrupt Mode Bit 1 23 1 P24 Interrupt Mode Bit 1 24 1 P25 Interrupt Mode Bit 1 25 1 P26 Interrupt Mode Bit 1 26 1 P27 Interrupt Mode Bit 1 27 1 P28 Interrupt Mode Bit 1 28 1 P29 Interrupt Mode Bit 1 29 1 P3 Interrupt Mode Bit 1 3 1 P30 Interrupt Mode Bit 1 30 1 P31 Interrupt Mode Bit 1 31 1 P4 Interrupt Mode Bit 1 4 1 P5 Interrupt Mode Bit 1 5 1 P6 Interrupt Mode Bit 1 6 1 P7 Interrupt Mode Bit 1 7 1 P8 Interrupt Mode Bit 1 8 1 P9 Interrupt Mode Bit 1 9 1 IMR12 Interrupt Mode Register 1 0x8C0 32 read-write n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 P1 Interrupt Mode Bit 1 1 1 P10 Interrupt Mode Bit 1 10 1 P11 Interrupt Mode Bit 1 11 1 P12 Interrupt Mode Bit 1 12 1 P13 Interrupt Mode Bit 1 13 1 P14 Interrupt Mode Bit 1 14 1 P15 Interrupt Mode Bit 1 15 1 P16 Interrupt Mode Bit 1 16 1 P17 Interrupt Mode Bit 1 17 1 P18 Interrupt Mode Bit 1 18 1 P19 Interrupt Mode Bit 1 19 1 P2 Interrupt Mode Bit 1 2 1 P20 Interrupt Mode Bit 1 20 1 P21 Interrupt Mode Bit 1 21 1 P22 Interrupt Mode Bit 1 22 1 P23 Interrupt Mode Bit 1 23 1 P24 Interrupt Mode Bit 1 24 1 P25 Interrupt Mode Bit 1 25 1 P26 Interrupt Mode Bit 1 26 1 P27 Interrupt Mode Bit 1 27 1 P28 Interrupt Mode Bit 1 28 1 P29 Interrupt Mode Bit 1 29 1 P3 Interrupt Mode Bit 1 3 1 P30 Interrupt Mode Bit 1 30 1 P31 Interrupt Mode Bit 1 31 1 P4 Interrupt Mode Bit 1 4 1 P5 Interrupt Mode Bit 1 5 1 P6 Interrupt Mode Bit 1 6 1 P7 Interrupt Mode Bit 1 7 1 P8 Interrupt Mode Bit 1 8 1 P9 Interrupt Mode Bit 1 9 1 IMR1C0 Interrupt Mode Register 1 - Clear 0x170 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only IMR1C1 Interrupt Mode Register 1 - Clear 0x428 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only IMR1C2 Interrupt Mode Register 1 - Clear 0x8E0 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only IMR1S0 Interrupt Mode Register 1 - Set 0x168 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only IMR1S1 Interrupt Mode Register 1 - Set 0x41C 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only IMR1S2 Interrupt Mode Register 1 - Set 0x8D0 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only IMR1T0 Interrupt Mode Register 1 - Toggle 0x178 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only IMR1T1 Interrupt Mode Register 1 - Toggle 0x434 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only IMR1T2 Interrupt Mode Register 1 - Toggle 0x8F0 32 write-only n 0x0 0x0 P0 Interrupt Mode Bit 1 0 1 write-only P1 Interrupt Mode Bit 1 1 1 write-only P10 Interrupt Mode Bit 1 10 1 write-only P11 Interrupt Mode Bit 1 11 1 write-only P12 Interrupt Mode Bit 1 12 1 write-only P13 Interrupt Mode Bit 1 13 1 write-only P14 Interrupt Mode Bit 1 14 1 write-only P15 Interrupt Mode Bit 1 15 1 write-only P16 Interrupt Mode Bit 1 16 1 write-only P17 Interrupt Mode Bit 1 17 1 write-only P18 Interrupt Mode Bit 1 18 1 write-only P19 Interrupt Mode Bit 1 19 1 write-only P2 Interrupt Mode Bit 1 2 1 write-only P20 Interrupt Mode Bit 1 20 1 write-only P21 Interrupt Mode Bit 1 21 1 write-only P22 Interrupt Mode Bit 1 22 1 write-only P23 Interrupt Mode Bit 1 23 1 write-only P24 Interrupt Mode Bit 1 24 1 write-only P25 Interrupt Mode Bit 1 25 1 write-only P26 Interrupt Mode Bit 1 26 1 write-only P27 Interrupt Mode Bit 1 27 1 write-only P28 Interrupt Mode Bit 1 28 1 write-only P29 Interrupt Mode Bit 1 29 1 write-only P3 Interrupt Mode Bit 1 3 1 write-only P30 Interrupt Mode Bit 1 30 1 write-only P31 Interrupt Mode Bit 1 31 1 write-only P4 Interrupt Mode Bit 1 4 1 write-only P5 Interrupt Mode Bit 1 5 1 write-only P6 Interrupt Mode Bit 1 6 1 write-only P7 Interrupt Mode Bit 1 7 1 write-only P8 Interrupt Mode Bit 1 8 1 write-only P9 Interrupt Mode Bit 1 9 1 write-only LOCK0 Lock Register 0x340 32 read-write n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCK1 Lock Register 0x6E0 32 read-write n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCK2 Lock Register 0xC80 32 read-write n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCKC0 Lock Register - Clear 0x350 32 write-only n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCKC1 Lock Register - Clear 0x6F8 32 write-only n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCKC2 Lock Register - Clear 0xCA0 32 write-only n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCKS0 Lock Register - Set 0x348 32 write-only n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCKS1 Lock Register - Set 0x6EC 32 write-only n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCKS2 Lock Register - Set 0xC90 32 write-only n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCKT0 Lock Register - Toggle 0x358 32 write-only n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCKT1 Lock Register - Toggle 0x704 32 write-only n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 LOCKT2 Lock Register - Toggle 0xCB0 32 write-only n 0x0 0x0 P0 Lock State 0 1 P1 Lock State 1 1 P10 Lock State 10 1 P11 Lock State 11 1 P12 Lock State 12 1 P13 Lock State 13 1 P14 Lock State 14 1 P15 Lock State 15 1 P16 Lock State 16 1 P17 Lock State 17 1 P18 Lock State 18 1 P19 Lock State 19 1 P2 Lock State 2 1 P20 Lock State 20 1 P21 Lock State 21 1 P22 Lock State 22 1 P23 Lock State 23 1 P24 Lock State 24 1 P25 Lock State 25 1 P26 Lock State 26 1 P27 Lock State 27 1 P28 Lock State 28 1 P29 Lock State 29 1 P3 Lock State 3 1 P30 Lock State 30 1 P31 Lock State 31 1 P4 Lock State 4 1 P5 Lock State 5 1 P6 Lock State 6 1 P7 Lock State 7 1 P8 Lock State 8 1 P9 Lock State 9 1 ODCR00 Output Driving Capability Register 0 0x200 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR01 Output Driving Capability Register 0 0x500 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR02 Output Driving Capability Register 0 0xA00 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR0C0 Output Driving Capability Register 0 - Clear 0x210 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR0C1 Output Driving Capability Register 0 - Clear 0x518 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR0C2 Output Driving Capability Register 0 - Clear 0xA20 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR0S0 Output Driving Capability Register 0 - Set 0x208 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR0S1 Output Driving Capability Register 0 - Set 0x50C 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR0S2 Output Driving Capability Register 0 - Set 0xA10 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR0T0 Output Driving Capability Register 0 - Toggle 0x218 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR0T1 Output Driving Capability Register 0 - Toggle 0x524 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR0T2 Output Driving Capability Register 0 - Toggle 0xA30 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 0 0 1 P1 Output Driving Capability Register Bit 0 1 1 P10 Output Driving Capability Register Bit 0 10 1 P11 Output Driving Capability Register Bit 0 11 1 P12 Output Driving Capability Register Bit 0 12 1 P13 Output Driving Capability Register Bit 0 13 1 P14 Output Driving Capability Register Bit 0 14 1 P15 Output Driving Capability Register Bit 0 15 1 P16 Output Driving Capability Register Bit 0 16 1 P17 Output Driving Capability Register Bit 0 17 1 P18 Output Driving Capability Register Bit 0 18 1 P19 Output Driving Capability Register Bit 0 19 1 P2 Output Driving Capability Register Bit 0 2 1 P20 Output Driving Capability Register Bit 0 20 1 P21 Output Driving Capability Register Bit 0 21 1 P22 Output Driving Capability Register Bit 0 22 1 P23 Output Driving Capability Register Bit 0 23 1 P24 Output Driving Capability Register Bit 0 24 1 P25 Output Driving Capability Register Bit 0 25 1 P26 Output Driving Capability Register Bit 0 26 1 P27 Output Driving Capability Register Bit 0 27 1 P28 Output Driving Capability Register Bit 0 28 1 P29 Output Driving Capability Register Bit 0 29 1 P3 Output Driving Capability Register Bit 0 3 1 P30 Output Driving Capability Register Bit 0 30 1 P31 Output Driving Capability Register Bit 0 31 1 P4 Output Driving Capability Register Bit 0 4 1 P5 Output Driving Capability Register Bit 0 5 1 P6 Output Driving Capability Register Bit 0 6 1 P7 Output Driving Capability Register Bit 0 7 1 P8 Output Driving Capability Register Bit 0 8 1 P9 Output Driving Capability Register Bit 0 9 1 ODCR10 Output Driving Capability Register 1 0x220 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR11 Output Driving Capability Register 1 0x530 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR12 Output Driving Capability Register 1 0xA40 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR1C0 Output Driving Capability Register 1 - Clear 0x230 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR1C1 Output Driving Capability Register 1 - Clear 0x548 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR1C2 Output Driving Capability Register 1 - Clear 0xA60 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR1S0 Output Driving Capability Register 1 - Set 0x228 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR1S1 Output Driving Capability Register 1 - Set 0x53C 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR1S2 Output Driving Capability Register 1 - Set 0xA50 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR1T0 Output Driving Capability Register 1 - Toggle 0x238 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR1T1 Output Driving Capability Register 1 - Toggle 0x554 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODCR1T2 Output Driving Capability Register 1 - Toggle 0xA70 32 read-write n 0x0 0x0 P0 Output Driving Capability Register Bit 1 0 1 P1 Output Driving Capability Register Bit 1 1 1 P10 Output Driving Capability Register Bit 1 10 1 P11 Output Driving Capability Register Bit 1 11 1 P12 Output Driving Capability Register Bit 1 12 1 P13 Output Driving Capability Register Bit 1 13 1 P14 Output Driving Capability Register Bit 1 14 1 P15 Output Driving Capability Register Bit 1 15 1 P16 Output Driving Capability Register Bit 1 16 1 P17 Output Driving Capability Register Bit 1 17 1 P18 Output Driving Capability Register Bit 1 18 1 P19 Output Driving Capability Register Bit 1 19 1 P2 Output Driving Capability Register Bit 1 2 1 P20 Output Driving Capability Register Bit 1 20 1 P21 Output Driving Capability Register Bit 1 21 1 P22 Output Driving Capability Register Bit 1 22 1 P23 Output Driving Capability Register Bit 1 23 1 P24 Output Driving Capability Register Bit 1 24 1 P25 Output Driving Capability Register Bit 1 25 1 P26 Output Driving Capability Register Bit 1 26 1 P27 Output Driving Capability Register Bit 1 27 1 P28 Output Driving Capability Register Bit 1 28 1 P29 Output Driving Capability Register Bit 1 29 1 P3 Output Driving Capability Register Bit 1 3 1 P30 Output Driving Capability Register Bit 1 30 1 P31 Output Driving Capability Register Bit 1 31 1 P4 Output Driving Capability Register Bit 1 4 1 P5 Output Driving Capability Register Bit 1 5 1 P6 Output Driving Capability Register Bit 1 6 1 P7 Output Driving Capability Register Bit 1 7 1 P8 Output Driving Capability Register Bit 1 8 1 P9 Output Driving Capability Register Bit 1 9 1 ODER0 Output Driver Enable Register 0x80 32 read-write n 0x0 0x0 P0 Output Driver Enable 0 1 P1 Output Driver Enable 1 1 P10 Output Driver Enable 10 1 P11 Output Driver Enable 11 1 P12 Output Driver Enable 12 1 P13 Output Driver Enable 13 1 P14 Output Driver Enable 14 1 P15 Output Driver Enable 15 1 P16 Output Driver Enable 16 1 P17 Output Driver Enable 17 1 P18 Output Driver Enable 18 1 P19 Output Driver Enable 19 1 P2 Output Driver Enable 2 1 P20 Output Driver Enable 20 1 P21 Output Driver Enable 21 1 P22 Output Driver Enable 22 1 P23 Output Driver Enable 23 1 P24 Output Driver Enable 24 1 P25 Output Driver Enable 25 1 P26 Output Driver Enable 26 1 P27 Output Driver Enable 27 1 P28 Output Driver Enable 28 1 P29 Output Driver Enable 29 1 P3 Output Driver Enable 3 1 P30 Output Driver Enable 30 1 P31 Output Driver Enable 31 1 P4 Output Driver Enable 4 1 P5 Output Driver Enable 5 1 P6 Output Driver Enable 6 1 P7 Output Driver Enable 7 1 P8 Output Driver Enable 8 1 P9 Output Driver Enable 9 1 ODER1 Output Driver Enable Register 0x2C0 32 read-write n 0x0 0x0 P0 Output Driver Enable 0 1 P1 Output Driver Enable 1 1 P10 Output Driver Enable 10 1 P11 Output Driver Enable 11 1 P12 Output Driver Enable 12 1 P13 Output Driver Enable 13 1 P14 Output Driver Enable 14 1 P15 Output Driver Enable 15 1 P16 Output Driver Enable 16 1 P17 Output Driver Enable 17 1 P18 Output Driver Enable 18 1 P19 Output Driver Enable 19 1 P2 Output Driver Enable 2 1 P20 Output Driver Enable 20 1 P21 Output Driver Enable 21 1 P22 Output Driver Enable 22 1 P23 Output Driver Enable 23 1 P24 Output Driver Enable 24 1 P25 Output Driver Enable 25 1 P26 Output Driver Enable 26 1 P27 Output Driver Enable 27 1 P28 Output Driver Enable 28 1 P29 Output Driver Enable 29 1 P3 Output Driver Enable 3 1 P30 Output Driver Enable 30 1 P31 Output Driver Enable 31 1 P4 Output Driver Enable 4 1 P5 Output Driver Enable 5 1 P6 Output Driver Enable 6 1 P7 Output Driver Enable 7 1 P8 Output Driver Enable 8 1 P9 Output Driver Enable 9 1 ODER2 Output Driver Enable Register 0x700 32 read-write n 0x0 0x0 P0 Output Driver Enable 0 1 P1 Output Driver Enable 1 1 P10 Output Driver Enable 10 1 P11 Output Driver Enable 11 1 P12 Output Driver Enable 12 1 P13 Output Driver Enable 13 1 P14 Output Driver Enable 14 1 P15 Output Driver Enable 15 1 P16 Output Driver Enable 16 1 P17 Output Driver Enable 17 1 P18 Output Driver Enable 18 1 P19 Output Driver Enable 19 1 P2 Output Driver Enable 2 1 P20 Output Driver Enable 20 1 P21 Output Driver Enable 21 1 P22 Output Driver Enable 22 1 P23 Output Driver Enable 23 1 P24 Output Driver Enable 24 1 P25 Output Driver Enable 25 1 P26 Output Driver Enable 26 1 P27 Output Driver Enable 27 1 P28 Output Driver Enable 28 1 P29 Output Driver Enable 29 1 P3 Output Driver Enable 3 1 P30 Output Driver Enable 30 1 P31 Output Driver Enable 31 1 P4 Output Driver Enable 4 1 P5 Output Driver Enable 5 1 P6 Output Driver Enable 6 1 P7 Output Driver Enable 7 1 P8 Output Driver Enable 8 1 P9 Output Driver Enable 9 1 ODERC0 Output Driver Enable Register - Clear 0x90 32 write-only n 0x0 0x0 P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P2 Output Driver Enable 2 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P3 Output Driver Enable 3 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only ODERC1 Output Driver Enable Register - Clear 0x2D8 32 write-only n 0x0 0x0 P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P2 Output Driver Enable 2 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P3 Output Driver Enable 3 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only ODERC2 Output Driver Enable Register - Clear 0x720 32 write-only n 0x0 0x0 P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P2 Output Driver Enable 2 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P3 Output Driver Enable 3 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only ODERS0 Output Driver Enable Register - Set 0x88 32 write-only n 0x0 0x0 P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P2 Output Driver Enable 2 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P3 Output Driver Enable 3 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only ODERS1 Output Driver Enable Register - Set 0x2CC 32 write-only n 0x0 0x0 P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P2 Output Driver Enable 2 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P3 Output Driver Enable 3 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only ODERS2 Output Driver Enable Register - Set 0x710 32 write-only n 0x0 0x0 P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P2 Output Driver Enable 2 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P3 Output Driver Enable 3 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only ODERT0 Output Driver Enable Register - Toggle 0x98 32 write-only n 0x0 0x0 P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P2 Output Driver Enable 2 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P3 Output Driver Enable 3 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only ODERT1 Output Driver Enable Register - Toggle 0x2E4 32 write-only n 0x0 0x0 P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P2 Output Driver Enable 2 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P3 Output Driver Enable 3 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only ODERT2 Output Driver Enable Register - Toggle 0x730 32 write-only n 0x0 0x0 P0 Output Driver Enable 0 1 write-only P1 Output Driver Enable 1 1 write-only P10 Output Driver Enable 10 1 write-only P11 Output Driver Enable 11 1 write-only P12 Output Driver Enable 12 1 write-only P13 Output Driver Enable 13 1 write-only P14 Output Driver Enable 14 1 write-only P15 Output Driver Enable 15 1 write-only P16 Output Driver Enable 16 1 write-only P17 Output Driver Enable 17 1 write-only P18 Output Driver Enable 18 1 write-only P19 Output Driver Enable 19 1 write-only P2 Output Driver Enable 2 1 write-only P20 Output Driver Enable 20 1 write-only P21 Output Driver Enable 21 1 write-only P22 Output Driver Enable 22 1 write-only P23 Output Driver Enable 23 1 write-only P24 Output Driver Enable 24 1 write-only P25 Output Driver Enable 25 1 write-only P26 Output Driver Enable 26 1 write-only P27 Output Driver Enable 27 1 write-only P28 Output Driver Enable 28 1 write-only P29 Output Driver Enable 29 1 write-only P3 Output Driver Enable 3 1 write-only P30 Output Driver Enable 30 1 write-only P31 Output Driver Enable 31 1 write-only P4 Output Driver Enable 4 1 write-only P5 Output Driver Enable 5 1 write-only P6 Output Driver Enable 6 1 write-only P7 Output Driver Enable 7 1 write-only P8 Output Driver Enable 8 1 write-only P9 Output Driver Enable 9 1 write-only ODMER0 Open Drain Mode Register 0x1C0 32 read-write n 0x0 0x0 P0 Open Drain Mode Enable 0 1 P1 Open Drain Mode Enable 1 1 P10 Open Drain Mode Enable 10 1 P11 Open Drain Mode Enable 11 1 P12 Open Drain Mode Enable 12 1 P13 Open Drain Mode Enable 13 1 P14 Open Drain Mode Enable 14 1 P15 Open Drain Mode Enable 15 1 P16 Open Drain Mode Enable 16 1 P17 Open Drain Mode Enable 17 1 P18 Open Drain Mode Enable 18 1 P19 Open Drain Mode Enable 19 1 P2 Open Drain Mode Enable 2 1 P20 Open Drain Mode Enable 20 1 P21 Open Drain Mode Enable 21 1 P22 Open Drain Mode Enable 22 1 P23 Open Drain Mode Enable 23 1 P24 Open Drain Mode Enable 24 1 P25 Open Drain Mode Enable 25 1 P26 Open Drain Mode Enable 26 1 P27 Open Drain Mode Enable 27 1 P28 Open Drain Mode Enable 28 1 P29 Open Drain Mode Enable 29 1 P3 Open Drain Mode Enable 3 1 P30 Open Drain Mode Enable 30 1 P31 Open Drain Mode Enable 31 1 P4 Open Drain Mode Enable 4 1 P5 Open Drain Mode Enable 5 1 P6 Open Drain Mode Enable 6 1 P7 Open Drain Mode Enable 7 1 P8 Open Drain Mode Enable 8 1 P9 Open Drain Mode Enable 9 1 ODMER1 Open Drain Mode Register 0x4A0 32 read-write n 0x0 0x0 P0 Open Drain Mode Enable 0 1 P1 Open Drain Mode Enable 1 1 P10 Open Drain Mode Enable 10 1 P11 Open Drain Mode Enable 11 1 P12 Open Drain Mode Enable 12 1 P13 Open Drain Mode Enable 13 1 P14 Open Drain Mode Enable 14 1 P15 Open Drain Mode Enable 15 1 P16 Open Drain Mode Enable 16 1 P17 Open Drain Mode Enable 17 1 P18 Open Drain Mode Enable 18 1 P19 Open Drain Mode Enable 19 1 P2 Open Drain Mode Enable 2 1 P20 Open Drain Mode Enable 20 1 P21 Open Drain Mode Enable 21 1 P22 Open Drain Mode Enable 22 1 P23 Open Drain Mode Enable 23 1 P24 Open Drain Mode Enable 24 1 P25 Open Drain Mode Enable 25 1 P26 Open Drain Mode Enable 26 1 P27 Open Drain Mode Enable 27 1 P28 Open Drain Mode Enable 28 1 P29 Open Drain Mode Enable 29 1 P3 Open Drain Mode Enable 3 1 P30 Open Drain Mode Enable 30 1 P31 Open Drain Mode Enable 31 1 P4 Open Drain Mode Enable 4 1 P5 Open Drain Mode Enable 5 1 P6 Open Drain Mode Enable 6 1 P7 Open Drain Mode Enable 7 1 P8 Open Drain Mode Enable 8 1 P9 Open Drain Mode Enable 9 1 ODMER2 Open Drain Mode Register 0x980 32 read-write n 0x0 0x0 P0 Open Drain Mode Enable 0 1 P1 Open Drain Mode Enable 1 1 P10 Open Drain Mode Enable 10 1 P11 Open Drain Mode Enable 11 1 P12 Open Drain Mode Enable 12 1 P13 Open Drain Mode Enable 13 1 P14 Open Drain Mode Enable 14 1 P15 Open Drain Mode Enable 15 1 P16 Open Drain Mode Enable 16 1 P17 Open Drain Mode Enable 17 1 P18 Open Drain Mode Enable 18 1 P19 Open Drain Mode Enable 19 1 P2 Open Drain Mode Enable 2 1 P20 Open Drain Mode Enable 20 1 P21 Open Drain Mode Enable 21 1 P22 Open Drain Mode Enable 22 1 P23 Open Drain Mode Enable 23 1 P24 Open Drain Mode Enable 24 1 P25 Open Drain Mode Enable 25 1 P26 Open Drain Mode Enable 26 1 P27 Open Drain Mode Enable 27 1 P28 Open Drain Mode Enable 28 1 P29 Open Drain Mode Enable 29 1 P3 Open Drain Mode Enable 3 1 P30 Open Drain Mode Enable 30 1 P31 Open Drain Mode Enable 31 1 P4 Open Drain Mode Enable 4 1 P5 Open Drain Mode Enable 5 1 P6 Open Drain Mode Enable 6 1 P7 Open Drain Mode Enable 7 1 P8 Open Drain Mode Enable 8 1 P9 Open Drain Mode Enable 9 1 ODMERC0 Open Drain Mode Register - Clear 0x1D0 32 write-only n 0x0 0x0 P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P2 Open Drain Mode Enable 2 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P3 Open Drain Mode Enable 3 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only ODMERC1 Open Drain Mode Register - Clear 0x4B8 32 write-only n 0x0 0x0 P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P2 Open Drain Mode Enable 2 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P3 Open Drain Mode Enable 3 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only ODMERC2 Open Drain Mode Register - Clear 0x9A0 32 write-only n 0x0 0x0 P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P2 Open Drain Mode Enable 2 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P3 Open Drain Mode Enable 3 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only ODMERS0 Open Drain Mode Register - Set 0x1C8 32 write-only n 0x0 0x0 P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P2 Open Drain Mode Enable 2 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P3 Open Drain Mode Enable 3 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only ODMERS1 Open Drain Mode Register - Set 0x4AC 32 write-only n 0x0 0x0 P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P2 Open Drain Mode Enable 2 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P3 Open Drain Mode Enable 3 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only ODMERS2 Open Drain Mode Register - Set 0x990 32 write-only n 0x0 0x0 P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P2 Open Drain Mode Enable 2 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P3 Open Drain Mode Enable 3 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only ODMERT0 Open Drain Mode Register - Toggle 0x1D8 32 write-only n 0x0 0x0 P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P2 Open Drain Mode Enable 2 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P3 Open Drain Mode Enable 3 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only ODMERT1 Open Drain Mode Register - Toggle 0x4C4 32 write-only n 0x0 0x0 P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P2 Open Drain Mode Enable 2 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P3 Open Drain Mode Enable 3 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only ODMERT2 Open Drain Mode Register - Toggle 0x9B0 32 write-only n 0x0 0x0 P0 Open Drain Mode Enable 0 1 write-only P1 Open Drain Mode Enable 1 1 write-only P10 Open Drain Mode Enable 10 1 write-only P11 Open Drain Mode Enable 11 1 write-only P12 Open Drain Mode Enable 12 1 write-only P13 Open Drain Mode Enable 13 1 write-only P14 Open Drain Mode Enable 14 1 write-only P15 Open Drain Mode Enable 15 1 write-only P16 Open Drain Mode Enable 16 1 write-only P17 Open Drain Mode Enable 17 1 write-only P18 Open Drain Mode Enable 18 1 write-only P19 Open Drain Mode Enable 19 1 write-only P2 Open Drain Mode Enable 2 1 write-only P20 Open Drain Mode Enable 20 1 write-only P21 Open Drain Mode Enable 21 1 write-only P22 Open Drain Mode Enable 22 1 write-only P23 Open Drain Mode Enable 23 1 write-only P24 Open Drain Mode Enable 24 1 write-only P25 Open Drain Mode Enable 25 1 write-only P26 Open Drain Mode Enable 26 1 write-only P27 Open Drain Mode Enable 27 1 write-only P28 Open Drain Mode Enable 28 1 write-only P29 Open Drain Mode Enable 29 1 write-only P3 Open Drain Mode Enable 3 1 write-only P30 Open Drain Mode Enable 30 1 write-only P31 Open Drain Mode Enable 31 1 write-only P4 Open Drain Mode Enable 4 1 write-only P5 Open Drain Mode Enable 5 1 write-only P6 Open Drain Mode Enable 6 1 write-only P7 Open Drain Mode Enable 7 1 write-only P8 Open Drain Mode Enable 8 1 write-only P9 Open Drain Mode Enable 9 1 write-only OSRR00 Output Slew Rate Register 0 0x260 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR01 Output Slew Rate Register 0 0x590 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR02 Output Slew Rate Register 0 0xAC0 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR0C0 Output Slew Rate Register 0 - Clear 0x270 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR0C1 Output Slew Rate Register 0 - Clear 0x5A8 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR0C2 Output Slew Rate Register 0 - Clear 0xAE0 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR0S0 Output Slew Rate Register 0 - Set 0x268 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR0S1 Output Slew Rate Register 0 - Set 0x59C 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR0S2 Output Slew Rate Register 0 - Set 0xAD0 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR0T0 Output Slew Rate Register 0 - Toggle 0x278 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR0T1 Output Slew Rate Register 0 - Toggle 0x5B4 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OSRR0T2 Output Slew Rate Register 0 - Toggle 0xAF0 32 read-write n 0x0 0x0 P0 Output Slew Rate Control Enable 0 1 P1 Output Slew Rate Control Enable 1 1 P10 Output Slew Rate Control Enable 10 1 P11 Output Slew Rate Control Enable 11 1 P12 Output Slew Rate Control Enable 12 1 P13 Output Slew Rate Control Enable 13 1 P14 Output Slew Rate Control Enable 14 1 P15 Output Slew Rate Control Enable 15 1 P16 Output Slew Rate Control Enable 16 1 P17 Output Slew Rate Control Enable 17 1 P18 Output Slew Rate Control Enable 18 1 P19 Output Slew Rate Control Enable 19 1 P2 Output Slew Rate Control Enable 2 1 P20 Output Slew Rate Control Enable 20 1 P21 Output Slew Rate Control Enable 21 1 P22 Output Slew Rate Control Enable 22 1 P23 Output Slew Rate Control Enable 23 1 P24 Output Slew Rate Control Enable 24 1 P25 Output Slew Rate Control Enable 25 1 P26 Output Slew Rate Control Enable 26 1 P27 Output Slew Rate Control Enable 27 1 P28 Output Slew Rate Control Enable 28 1 P29 Output Slew Rate Control Enable 29 1 P3 Output Slew Rate Control Enable 3 1 P30 Output Slew Rate Control Enable 30 1 P31 Output Slew Rate Control Enable 31 1 P4 Output Slew Rate Control Enable 4 1 P5 Output Slew Rate Control Enable 5 1 P6 Output Slew Rate Control Enable 6 1 P7 Output Slew Rate Control Enable 7 1 P8 Output Slew Rate Control Enable 8 1 P9 Output Slew Rate Control Enable 9 1 OVR0 Output Value Register 0xA0 32 read-write n 0x0 0x0 P0 Output Value 0 1 P1 Output Value 1 1 P10 Output Value 10 1 P11 Output Value 11 1 P12 Output Value 12 1 P13 Output Value 13 1 P14 Output Value 14 1 P15 Output Value 15 1 P16 Output Value 16 1 P17 Output Value 17 1 P18 Output Value 18 1 P19 Output Value 19 1 P2 Output Value 2 1 P20 Output Value 20 1 P21 Output Value 21 1 P22 Output Value 22 1 P23 Output Value 23 1 P24 Output Value 24 1 P25 Output Value 25 1 P26 Output Value 26 1 P27 Output Value 27 1 P28 Output Value 28 1 P29 Output Value 29 1 P3 Output Value 3 1 P30 Output Value 30 1 P31 Output Value 31 1 P4 Output Value 4 1 P5 Output Value 5 1 P6 Output Value 6 1 P7 Output Value 7 1 P8 Output Value 8 1 P9 Output Value 9 1 OVR1 Output Value Register 0x2F0 32 read-write n 0x0 0x0 P0 Output Value 0 1 P1 Output Value 1 1 P10 Output Value 10 1 P11 Output Value 11 1 P12 Output Value 12 1 P13 Output Value 13 1 P14 Output Value 14 1 P15 Output Value 15 1 P16 Output Value 16 1 P17 Output Value 17 1 P18 Output Value 18 1 P19 Output Value 19 1 P2 Output Value 2 1 P20 Output Value 20 1 P21 Output Value 21 1 P22 Output Value 22 1 P23 Output Value 23 1 P24 Output Value 24 1 P25 Output Value 25 1 P26 Output Value 26 1 P27 Output Value 27 1 P28 Output Value 28 1 P29 Output Value 29 1 P3 Output Value 3 1 P30 Output Value 30 1 P31 Output Value 31 1 P4 Output Value 4 1 P5 Output Value 5 1 P6 Output Value 6 1 P7 Output Value 7 1 P8 Output Value 8 1 P9 Output Value 9 1 OVR2 Output Value Register 0x740 32 read-write n 0x0 0x0 P0 Output Value 0 1 P1 Output Value 1 1 P10 Output Value 10 1 P11 Output Value 11 1 P12 Output Value 12 1 P13 Output Value 13 1 P14 Output Value 14 1 P15 Output Value 15 1 P16 Output Value 16 1 P17 Output Value 17 1 P18 Output Value 18 1 P19 Output Value 19 1 P2 Output Value 2 1 P20 Output Value 20 1 P21 Output Value 21 1 P22 Output Value 22 1 P23 Output Value 23 1 P24 Output Value 24 1 P25 Output Value 25 1 P26 Output Value 26 1 P27 Output Value 27 1 P28 Output Value 28 1 P29 Output Value 29 1 P3 Output Value 3 1 P30 Output Value 30 1 P31 Output Value 31 1 P4 Output Value 4 1 P5 Output Value 5 1 P6 Output Value 6 1 P7 Output Value 7 1 P8 Output Value 8 1 P9 Output Value 9 1 OVRC0 Output Value Register - Clear 0xB0 32 write-only n 0x0 0x0 P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P2 Output Value 2 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P3 Output Value 3 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only OVRC1 Output Value Register - Clear 0x308 32 write-only n 0x0 0x0 P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P2 Output Value 2 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P3 Output Value 3 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only OVRC2 Output Value Register - Clear 0x760 32 write-only n 0x0 0x0 P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P2 Output Value 2 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P3 Output Value 3 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only OVRS0 Output Value Register - Set 0xA8 32 write-only n 0x0 0x0 P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P2 Output Value 2 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P3 Output Value 3 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only OVRS1 Output Value Register - Set 0x2FC 32 write-only n 0x0 0x0 P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P2 Output Value 2 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P3 Output Value 3 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only OVRS2 Output Value Register - Set 0x750 32 write-only n 0x0 0x0 P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P2 Output Value 2 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P3 Output Value 3 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only OVRT0 Output Value Register - Toggle 0xB8 32 write-only n 0x0 0x0 P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P2 Output Value 2 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P3 Output Value 3 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only OVRT1 Output Value Register - Toggle 0x314 32 write-only n 0x0 0x0 P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P2 Output Value 2 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P3 Output Value 3 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only OVRT2 Output Value Register - Toggle 0x770 32 write-only n 0x0 0x0 P0 Output Value 0 1 write-only P1 Output Value 1 1 write-only P10 Output Value 10 1 write-only P11 Output Value 11 1 write-only P12 Output Value 12 1 write-only P13 Output Value 13 1 write-only P14 Output Value 14 1 write-only P15 Output Value 15 1 write-only P16 Output Value 16 1 write-only P17 Output Value 17 1 write-only P18 Output Value 18 1 write-only P19 Output Value 19 1 write-only P2 Output Value 2 1 write-only P20 Output Value 20 1 write-only P21 Output Value 21 1 write-only P22 Output Value 22 1 write-only P23 Output Value 23 1 write-only P24 Output Value 24 1 write-only P25 Output Value 25 1 write-only P26 Output Value 26 1 write-only P27 Output Value 27 1 write-only P28 Output Value 28 1 write-only P29 Output Value 29 1 write-only P3 Output Value 3 1 write-only P30 Output Value 30 1 write-only P31 Output Value 31 1 write-only P4 Output Value 4 1 write-only P5 Output Value 5 1 write-only P6 Output Value 6 1 write-only P7 Output Value 7 1 write-only P8 Output Value 8 1 write-only P9 Output Value 9 1 write-only PARAMETER0 Parameter Register 0x3F0 32 read-only n 0x0 0x0 PARAMETER Parameter 0 32 PARAMETER1 Parameter Register 0x7E8 32 read-only n 0x0 0x0 PARAMETER Parameter 0 32 PARAMETER2 Parameter Register 0xDE0 32 read-only n 0x0 0x0 PARAMETER Parameter 0 32 PDER0 Pull-down Enable Register 0x100 32 read-write n 0x0 0x0 P0 Pull-down Enable 0 1 P1 Pull-down Enable 1 1 P10 Pull-down Enable 10 1 P11 Pull-down Enable 11 1 P12 Pull-down Enable 12 1 P13 Pull-down Enable 13 1 P14 Pull-down Enable 14 1 P15 Pull-down Enable 15 1 P16 Pull-down Enable 16 1 P17 Pull-down Enable 17 1 P18 Pull-down Enable 18 1 P19 Pull-down Enable 19 1 P2 Pull-down Enable 2 1 P20 Pull-down Enable 20 1 P21 Pull-down Enable 21 1 P22 Pull-down Enable 22 1 P23 Pull-down Enable 23 1 P24 Pull-down Enable 24 1 P25 Pull-down Enable 25 1 P26 Pull-down Enable 26 1 P27 Pull-down Enable 27 1 P28 Pull-down Enable 28 1 P29 Pull-down Enable 29 1 P3 Pull-down Enable 3 1 P30 Pull-down Enable 30 1 P31 Pull-down Enable 31 1 P4 Pull-down Enable 4 1 P5 Pull-down Enable 5 1 P6 Pull-down Enable 6 1 P7 Pull-down Enable 7 1 P8 Pull-down Enable 8 1 P9 Pull-down Enable 9 1 PDER1 Pull-down Enable Register 0x380 32 read-write n 0x0 0x0 P0 Pull-down Enable 0 1 P1 Pull-down Enable 1 1 P10 Pull-down Enable 10 1 P11 Pull-down Enable 11 1 P12 Pull-down Enable 12 1 P13 Pull-down Enable 13 1 P14 Pull-down Enable 14 1 P15 Pull-down Enable 15 1 P16 Pull-down Enable 16 1 P17 Pull-down Enable 17 1 P18 Pull-down Enable 18 1 P19 Pull-down Enable 19 1 P2 Pull-down Enable 2 1 P20 Pull-down Enable 20 1 P21 Pull-down Enable 21 1 P22 Pull-down Enable 22 1 P23 Pull-down Enable 23 1 P24 Pull-down Enable 24 1 P25 Pull-down Enable 25 1 P26 Pull-down Enable 26 1 P27 Pull-down Enable 27 1 P28 Pull-down Enable 28 1 P29 Pull-down Enable 29 1 P3 Pull-down Enable 3 1 P30 Pull-down Enable 30 1 P31 Pull-down Enable 31 1 P4 Pull-down Enable 4 1 P5 Pull-down Enable 5 1 P6 Pull-down Enable 6 1 P7 Pull-down Enable 7 1 P8 Pull-down Enable 8 1 P9 Pull-down Enable 9 1 PDER2 Pull-down Enable Register 0x800 32 read-write n 0x0 0x0 P0 Pull-down Enable 0 1 P1 Pull-down Enable 1 1 P10 Pull-down Enable 10 1 P11 Pull-down Enable 11 1 P12 Pull-down Enable 12 1 P13 Pull-down Enable 13 1 P14 Pull-down Enable 14 1 P15 Pull-down Enable 15 1 P16 Pull-down Enable 16 1 P17 Pull-down Enable 17 1 P18 Pull-down Enable 18 1 P19 Pull-down Enable 19 1 P2 Pull-down Enable 2 1 P20 Pull-down Enable 20 1 P21 Pull-down Enable 21 1 P22 Pull-down Enable 22 1 P23 Pull-down Enable 23 1 P24 Pull-down Enable 24 1 P25 Pull-down Enable 25 1 P26 Pull-down Enable 26 1 P27 Pull-down Enable 27 1 P28 Pull-down Enable 28 1 P29 Pull-down Enable 29 1 P3 Pull-down Enable 3 1 P30 Pull-down Enable 30 1 P31 Pull-down Enable 31 1 P4 Pull-down Enable 4 1 P5 Pull-down Enable 5 1 P6 Pull-down Enable 6 1 P7 Pull-down Enable 7 1 P8 Pull-down Enable 8 1 P9 Pull-down Enable 9 1 PDERC0 Pull-down Enable Register - Clear 0x110 32 write-only n 0x0 0x0 P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P2 Pull-down Enable 2 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P3 Pull-down Enable 3 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only PDERC1 Pull-down Enable Register - Clear 0x398 32 write-only n 0x0 0x0 P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P2 Pull-down Enable 2 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P3 Pull-down Enable 3 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only PDERC2 Pull-down Enable Register - Clear 0x820 32 write-only n 0x0 0x0 P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P2 Pull-down Enable 2 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P3 Pull-down Enable 3 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only PDERS0 Pull-down Enable Register - Set 0x108 32 write-only n 0x0 0x0 P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P2 Pull-down Enable 2 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P3 Pull-down Enable 3 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only PDERS1 Pull-down Enable Register - Set 0x38C 32 write-only n 0x0 0x0 P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P2 Pull-down Enable 2 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P3 Pull-down Enable 3 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only PDERS2 Pull-down Enable Register - Set 0x810 32 write-only n 0x0 0x0 P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P2 Pull-down Enable 2 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P3 Pull-down Enable 3 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only PDERT0 Pull-down Enable Register - Toggle 0x118 32 write-only n 0x0 0x0 P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P2 Pull-down Enable 2 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P3 Pull-down Enable 3 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only PDERT1 Pull-down Enable Register - Toggle 0x3A4 32 write-only n 0x0 0x0 P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P2 Pull-down Enable 2 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P3 Pull-down Enable 3 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only PDERT2 Pull-down Enable Register - Toggle 0x830 32 write-only n 0x0 0x0 P0 Pull-down Enable 0 1 write-only P1 Pull-down Enable 1 1 write-only P10 Pull-down Enable 10 1 write-only P11 Pull-down Enable 11 1 write-only P12 Pull-down Enable 12 1 write-only P13 Pull-down Enable 13 1 write-only P14 Pull-down Enable 14 1 write-only P15 Pull-down Enable 15 1 write-only P16 Pull-down Enable 16 1 write-only P17 Pull-down Enable 17 1 write-only P18 Pull-down Enable 18 1 write-only P19 Pull-down Enable 19 1 write-only P2 Pull-down Enable 2 1 write-only P20 Pull-down Enable 20 1 write-only P21 Pull-down Enable 21 1 write-only P22 Pull-down Enable 22 1 write-only P23 Pull-down Enable 23 1 write-only P24 Pull-down Enable 24 1 write-only P25 Pull-down Enable 25 1 write-only P26 Pull-down Enable 26 1 write-only P27 Pull-down Enable 27 1 write-only P28 Pull-down Enable 28 1 write-only P29 Pull-down Enable 29 1 write-only P3 Pull-down Enable 3 1 write-only P30 Pull-down Enable 30 1 write-only P31 Pull-down Enable 31 1 write-only P4 Pull-down Enable 4 1 write-only P5 Pull-down Enable 5 1 write-only P6 Pull-down Enable 6 1 write-only P7 Pull-down Enable 7 1 write-only P8 Pull-down Enable 8 1 write-only P9 Pull-down Enable 9 1 write-only PMR00 Peripheral Mux Register 0 0x20 32 read-write n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 P1 Peripheral Multiplexer Select bit 0 1 1 P10 Peripheral Multiplexer Select bit 0 10 1 P11 Peripheral Multiplexer Select bit 0 11 1 P12 Peripheral Multiplexer Select bit 0 12 1 P13 Peripheral Multiplexer Select bit 0 13 1 P14 Peripheral Multiplexer Select bit 0 14 1 P15 Peripheral Multiplexer Select bit 0 15 1 P16 Peripheral Multiplexer Select bit 0 16 1 P17 Peripheral Multiplexer Select bit 0 17 1 P18 Peripheral Multiplexer Select bit 0 18 1 P19 Peripheral Multiplexer Select bit 0 19 1 P2 Peripheral Multiplexer Select bit 0 2 1 P20 Peripheral Multiplexer Select bit 0 20 1 P21 Peripheral Multiplexer Select bit 0 21 1 P22 Peripheral Multiplexer Select bit 0 22 1 P23 Peripheral Multiplexer Select bit 0 23 1 P24 Peripheral Multiplexer Select bit 0 24 1 P25 Peripheral Multiplexer Select bit 0 25 1 P26 Peripheral Multiplexer Select bit 0 26 1 P27 Peripheral Multiplexer Select bit 0 27 1 P28 Peripheral Multiplexer Select bit 0 28 1 P29 Peripheral Multiplexer Select bit 0 29 1 P3 Peripheral Multiplexer Select bit 0 3 1 P30 Peripheral Multiplexer Select bit 0 30 1 P31 Peripheral Multiplexer Select bit 0 31 1 P4 Peripheral Multiplexer Select bit 0 4 1 P5 Peripheral Multiplexer Select bit 0 5 1 P6 Peripheral Multiplexer Select bit 0 6 1 P7 Peripheral Multiplexer Select bit 0 7 1 P8 Peripheral Multiplexer Select bit 0 8 1 P9 Peripheral Multiplexer Select bit 0 9 1 PMR01 Peripheral Mux Register 0 0x230 32 read-write n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 P1 Peripheral Multiplexer Select bit 0 1 1 P10 Peripheral Multiplexer Select bit 0 10 1 P11 Peripheral Multiplexer Select bit 0 11 1 P12 Peripheral Multiplexer Select bit 0 12 1 P13 Peripheral Multiplexer Select bit 0 13 1 P14 Peripheral Multiplexer Select bit 0 14 1 P15 Peripheral Multiplexer Select bit 0 15 1 P16 Peripheral Multiplexer Select bit 0 16 1 P17 Peripheral Multiplexer Select bit 0 17 1 P18 Peripheral Multiplexer Select bit 0 18 1 P19 Peripheral Multiplexer Select bit 0 19 1 P2 Peripheral Multiplexer Select bit 0 2 1 P20 Peripheral Multiplexer Select bit 0 20 1 P21 Peripheral Multiplexer Select bit 0 21 1 P22 Peripheral Multiplexer Select bit 0 22 1 P23 Peripheral Multiplexer Select bit 0 23 1 P24 Peripheral Multiplexer Select bit 0 24 1 P25 Peripheral Multiplexer Select bit 0 25 1 P26 Peripheral Multiplexer Select bit 0 26 1 P27 Peripheral Multiplexer Select bit 0 27 1 P28 Peripheral Multiplexer Select bit 0 28 1 P29 Peripheral Multiplexer Select bit 0 29 1 P3 Peripheral Multiplexer Select bit 0 3 1 P30 Peripheral Multiplexer Select bit 0 30 1 P31 Peripheral Multiplexer Select bit 0 31 1 P4 Peripheral Multiplexer Select bit 0 4 1 P5 Peripheral Multiplexer Select bit 0 5 1 P6 Peripheral Multiplexer Select bit 0 6 1 P7 Peripheral Multiplexer Select bit 0 7 1 P8 Peripheral Multiplexer Select bit 0 8 1 P9 Peripheral Multiplexer Select bit 0 9 1 PMR02 Peripheral Mux Register 0 0x640 32 read-write n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 P1 Peripheral Multiplexer Select bit 0 1 1 P10 Peripheral Multiplexer Select bit 0 10 1 P11 Peripheral Multiplexer Select bit 0 11 1 P12 Peripheral Multiplexer Select bit 0 12 1 P13 Peripheral Multiplexer Select bit 0 13 1 P14 Peripheral Multiplexer Select bit 0 14 1 P15 Peripheral Multiplexer Select bit 0 15 1 P16 Peripheral Multiplexer Select bit 0 16 1 P17 Peripheral Multiplexer Select bit 0 17 1 P18 Peripheral Multiplexer Select bit 0 18 1 P19 Peripheral Multiplexer Select bit 0 19 1 P2 Peripheral Multiplexer Select bit 0 2 1 P20 Peripheral Multiplexer Select bit 0 20 1 P21 Peripheral Multiplexer Select bit 0 21 1 P22 Peripheral Multiplexer Select bit 0 22 1 P23 Peripheral Multiplexer Select bit 0 23 1 P24 Peripheral Multiplexer Select bit 0 24 1 P25 Peripheral Multiplexer Select bit 0 25 1 P26 Peripheral Multiplexer Select bit 0 26 1 P27 Peripheral Multiplexer Select bit 0 27 1 P28 Peripheral Multiplexer Select bit 0 28 1 P29 Peripheral Multiplexer Select bit 0 29 1 P3 Peripheral Multiplexer Select bit 0 3 1 P30 Peripheral Multiplexer Select bit 0 30 1 P31 Peripheral Multiplexer Select bit 0 31 1 P4 Peripheral Multiplexer Select bit 0 4 1 P5 Peripheral Multiplexer Select bit 0 5 1 P6 Peripheral Multiplexer Select bit 0 6 1 P7 Peripheral Multiplexer Select bit 0 7 1 P8 Peripheral Multiplexer Select bit 0 8 1 P9 Peripheral Multiplexer Select bit 0 9 1 PMR0C0 Peripheral Mux Register 0 - Clear 0x30 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only PMR0C1 Peripheral Mux Register 0 - Clear 0x248 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only PMR0C2 Peripheral Mux Register 0 - Clear 0x660 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only PMR0S0 Peripheral Mux Register 0 - Set 0x28 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only PMR0S1 Peripheral Mux Register 0 - Set 0x23C 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only PMR0S2 Peripheral Mux Register 0 - Set 0x650 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only PMR0T0 Peripheral Mux Register 0 - Toggle 0x38 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only PMR0T1 Peripheral Mux Register 0 - Toggle 0x254 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only PMR0T2 Peripheral Mux Register 0 - Toggle 0x670 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 0 0 1 write-only P1 Peripheral Multiplexer Select bit 0 1 1 write-only P10 Peripheral Multiplexer Select bit 0 10 1 write-only P11 Peripheral Multiplexer Select bit 0 11 1 write-only P12 Peripheral Multiplexer Select bit 0 12 1 write-only P13 Peripheral Multiplexer Select bit 0 13 1 write-only P14 Peripheral Multiplexer Select bit 0 14 1 write-only P15 Peripheral Multiplexer Select bit 0 15 1 write-only P16 Peripheral Multiplexer Select bit 0 16 1 write-only P17 Peripheral Multiplexer Select bit 0 17 1 write-only P18 Peripheral Multiplexer Select bit 0 18 1 write-only P19 Peripheral Multiplexer Select bit 0 19 1 write-only P2 Peripheral Multiplexer Select bit 0 2 1 write-only P20 Peripheral Multiplexer Select bit 0 20 1 write-only P21 Peripheral Multiplexer Select bit 0 21 1 write-only P22 Peripheral Multiplexer Select bit 0 22 1 write-only P23 Peripheral Multiplexer Select bit 0 23 1 write-only P24 Peripheral Multiplexer Select bit 0 24 1 write-only P25 Peripheral Multiplexer Select bit 0 25 1 write-only P26 Peripheral Multiplexer Select bit 0 26 1 write-only P27 Peripheral Multiplexer Select bit 0 27 1 write-only P28 Peripheral Multiplexer Select bit 0 28 1 write-only P29 Peripheral Multiplexer Select bit 0 29 1 write-only P3 Peripheral Multiplexer Select bit 0 3 1 write-only P30 Peripheral Multiplexer Select bit 0 30 1 write-only P31 Peripheral Multiplexer Select bit 0 31 1 write-only P4 Peripheral Multiplexer Select bit 0 4 1 write-only P5 Peripheral Multiplexer Select bit 0 5 1 write-only P6 Peripheral Multiplexer Select bit 0 6 1 write-only P7 Peripheral Multiplexer Select bit 0 7 1 write-only P8 Peripheral Multiplexer Select bit 0 8 1 write-only P9 Peripheral Multiplexer Select bit 0 9 1 write-only PMR10 Peripheral Mux Register 1 0x40 32 read-write n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 P1 Peripheral Multiplexer Select bit 1 1 1 P10 Peripheral Multiplexer Select bit 1 10 1 P11 Peripheral Multiplexer Select bit 1 11 1 P12 Peripheral Multiplexer Select bit 1 12 1 P13 Peripheral Multiplexer Select bit 1 13 1 P14 Peripheral Multiplexer Select bit 1 14 1 P15 Peripheral Multiplexer Select bit 1 15 1 P16 Peripheral Multiplexer Select bit 1 16 1 P17 Peripheral Multiplexer Select bit 1 17 1 P18 Peripheral Multiplexer Select bit 1 18 1 P19 Peripheral Multiplexer Select bit 1 19 1 P2 Peripheral Multiplexer Select bit 1 2 1 P20 Peripheral Multiplexer Select bit 1 20 1 P21 Peripheral Multiplexer Select bit 1 21 1 P22 Peripheral Multiplexer Select bit 1 22 1 P23 Peripheral Multiplexer Select bit 1 23 1 P24 Peripheral Multiplexer Select bit 1 24 1 P25 Peripheral Multiplexer Select bit 1 25 1 P26 Peripheral Multiplexer Select bit 1 26 1 P27 Peripheral Multiplexer Select bit 1 27 1 P28 Peripheral Multiplexer Select bit 1 28 1 P29 Peripheral Multiplexer Select bit 1 29 1 P3 Peripheral Multiplexer Select bit 1 3 1 P30 Peripheral Multiplexer Select bit 1 30 1 P31 Peripheral Multiplexer Select bit 1 31 1 P4 Peripheral Multiplexer Select bit 1 4 1 P5 Peripheral Multiplexer Select bit 1 5 1 P6 Peripheral Multiplexer Select bit 1 6 1 P7 Peripheral Multiplexer Select bit 1 7 1 P8 Peripheral Multiplexer Select bit 1 8 1 P9 Peripheral Multiplexer Select bit 1 9 1 PMR11 Peripheral Mux Register 1 0x260 32 read-write n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 P1 Peripheral Multiplexer Select bit 1 1 1 P10 Peripheral Multiplexer Select bit 1 10 1 P11 Peripheral Multiplexer Select bit 1 11 1 P12 Peripheral Multiplexer Select bit 1 12 1 P13 Peripheral Multiplexer Select bit 1 13 1 P14 Peripheral Multiplexer Select bit 1 14 1 P15 Peripheral Multiplexer Select bit 1 15 1 P16 Peripheral Multiplexer Select bit 1 16 1 P17 Peripheral Multiplexer Select bit 1 17 1 P18 Peripheral Multiplexer Select bit 1 18 1 P19 Peripheral Multiplexer Select bit 1 19 1 P2 Peripheral Multiplexer Select bit 1 2 1 P20 Peripheral Multiplexer Select bit 1 20 1 P21 Peripheral Multiplexer Select bit 1 21 1 P22 Peripheral Multiplexer Select bit 1 22 1 P23 Peripheral Multiplexer Select bit 1 23 1 P24 Peripheral Multiplexer Select bit 1 24 1 P25 Peripheral Multiplexer Select bit 1 25 1 P26 Peripheral Multiplexer Select bit 1 26 1 P27 Peripheral Multiplexer Select bit 1 27 1 P28 Peripheral Multiplexer Select bit 1 28 1 P29 Peripheral Multiplexer Select bit 1 29 1 P3 Peripheral Multiplexer Select bit 1 3 1 P30 Peripheral Multiplexer Select bit 1 30 1 P31 Peripheral Multiplexer Select bit 1 31 1 P4 Peripheral Multiplexer Select bit 1 4 1 P5 Peripheral Multiplexer Select bit 1 5 1 P6 Peripheral Multiplexer Select bit 1 6 1 P7 Peripheral Multiplexer Select bit 1 7 1 P8 Peripheral Multiplexer Select bit 1 8 1 P9 Peripheral Multiplexer Select bit 1 9 1 PMR12 Peripheral Mux Register 1 0x680 32 read-write n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 P1 Peripheral Multiplexer Select bit 1 1 1 P10 Peripheral Multiplexer Select bit 1 10 1 P11 Peripheral Multiplexer Select bit 1 11 1 P12 Peripheral Multiplexer Select bit 1 12 1 P13 Peripheral Multiplexer Select bit 1 13 1 P14 Peripheral Multiplexer Select bit 1 14 1 P15 Peripheral Multiplexer Select bit 1 15 1 P16 Peripheral Multiplexer Select bit 1 16 1 P17 Peripheral Multiplexer Select bit 1 17 1 P18 Peripheral Multiplexer Select bit 1 18 1 P19 Peripheral Multiplexer Select bit 1 19 1 P2 Peripheral Multiplexer Select bit 1 2 1 P20 Peripheral Multiplexer Select bit 1 20 1 P21 Peripheral Multiplexer Select bit 1 21 1 P22 Peripheral Multiplexer Select bit 1 22 1 P23 Peripheral Multiplexer Select bit 1 23 1 P24 Peripheral Multiplexer Select bit 1 24 1 P25 Peripheral Multiplexer Select bit 1 25 1 P26 Peripheral Multiplexer Select bit 1 26 1 P27 Peripheral Multiplexer Select bit 1 27 1 P28 Peripheral Multiplexer Select bit 1 28 1 P29 Peripheral Multiplexer Select bit 1 29 1 P3 Peripheral Multiplexer Select bit 1 3 1 P30 Peripheral Multiplexer Select bit 1 30 1 P31 Peripheral Multiplexer Select bit 1 31 1 P4 Peripheral Multiplexer Select bit 1 4 1 P5 Peripheral Multiplexer Select bit 1 5 1 P6 Peripheral Multiplexer Select bit 1 6 1 P7 Peripheral Multiplexer Select bit 1 7 1 P8 Peripheral Multiplexer Select bit 1 8 1 P9 Peripheral Multiplexer Select bit 1 9 1 PMR1C0 Peripheral Mux Register 1 - Clear 0x50 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only PMR1C1 Peripheral Mux Register 1 - Clear 0x278 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only PMR1C2 Peripheral Mux Register 1 - Clear 0x6A0 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only PMR1S0 Peripheral Mux Register 1 - Set 0x48 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only PMR1S1 Peripheral Mux Register 1 - Set 0x26C 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only PMR1S2 Peripheral Mux Register 1 - Set 0x690 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only PMR1T0 Peripheral Mux Register 1 - Toggle 0x58 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only PMR1T1 Peripheral Mux Register 1 - Toggle 0x284 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only PMR1T2 Peripheral Mux Register 1 - Toggle 0x6B0 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 1 0 1 write-only P1 Peripheral Multiplexer Select bit 1 1 1 write-only P10 Peripheral Multiplexer Select bit 1 10 1 write-only P11 Peripheral Multiplexer Select bit 1 11 1 write-only P12 Peripheral Multiplexer Select bit 1 12 1 write-only P13 Peripheral Multiplexer Select bit 1 13 1 write-only P14 Peripheral Multiplexer Select bit 1 14 1 write-only P15 Peripheral Multiplexer Select bit 1 15 1 write-only P16 Peripheral Multiplexer Select bit 1 16 1 write-only P17 Peripheral Multiplexer Select bit 1 17 1 write-only P18 Peripheral Multiplexer Select bit 1 18 1 write-only P19 Peripheral Multiplexer Select bit 1 19 1 write-only P2 Peripheral Multiplexer Select bit 1 2 1 write-only P20 Peripheral Multiplexer Select bit 1 20 1 write-only P21 Peripheral Multiplexer Select bit 1 21 1 write-only P22 Peripheral Multiplexer Select bit 1 22 1 write-only P23 Peripheral Multiplexer Select bit 1 23 1 write-only P24 Peripheral Multiplexer Select bit 1 24 1 write-only P25 Peripheral Multiplexer Select bit 1 25 1 write-only P26 Peripheral Multiplexer Select bit 1 26 1 write-only P27 Peripheral Multiplexer Select bit 1 27 1 write-only P28 Peripheral Multiplexer Select bit 1 28 1 write-only P29 Peripheral Multiplexer Select bit 1 29 1 write-only P3 Peripheral Multiplexer Select bit 1 3 1 write-only P30 Peripheral Multiplexer Select bit 1 30 1 write-only P31 Peripheral Multiplexer Select bit 1 31 1 write-only P4 Peripheral Multiplexer Select bit 1 4 1 write-only P5 Peripheral Multiplexer Select bit 1 5 1 write-only P6 Peripheral Multiplexer Select bit 1 6 1 write-only P7 Peripheral Multiplexer Select bit 1 7 1 write-only P8 Peripheral Multiplexer Select bit 1 8 1 write-only P9 Peripheral Multiplexer Select bit 1 9 1 write-only PMR20 Peripheral Mux Register 2 0x60 32 read-write n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 P1 Peripheral Multiplexer Select bit 2 1 1 P10 Peripheral Multiplexer Select bit 2 10 1 P11 Peripheral Multiplexer Select bit 2 11 1 P12 Peripheral Multiplexer Select bit 2 12 1 P13 Peripheral Multiplexer Select bit 2 13 1 P14 Peripheral Multiplexer Select bit 2 14 1 P15 Peripheral Multiplexer Select bit 2 15 1 P16 Peripheral Multiplexer Select bit 2 16 1 P17 Peripheral Multiplexer Select bit 2 17 1 P18 Peripheral Multiplexer Select bit 2 18 1 P19 Peripheral Multiplexer Select bit 2 19 1 P2 Peripheral Multiplexer Select bit 2 2 1 P20 Peripheral Multiplexer Select bit 2 20 1 P21 Peripheral Multiplexer Select bit 2 21 1 P22 Peripheral Multiplexer Select bit 2 22 1 P23 Peripheral Multiplexer Select bit 2 23 1 P24 Peripheral Multiplexer Select bit 2 24 1 P25 Peripheral Multiplexer Select bit 2 25 1 P26 Peripheral Multiplexer Select bit 2 26 1 P27 Peripheral Multiplexer Select bit 2 27 1 P28 Peripheral Multiplexer Select bit 2 28 1 P29 Peripheral Multiplexer Select bit 2 29 1 P3 Peripheral Multiplexer Select bit 2 3 1 P30 Peripheral Multiplexer Select bit 2 30 1 P31 Peripheral Multiplexer Select bit 2 31 1 P4 Peripheral Multiplexer Select bit 2 4 1 P5 Peripheral Multiplexer Select bit 2 5 1 P6 Peripheral Multiplexer Select bit 2 6 1 P7 Peripheral Multiplexer Select bit 2 7 1 P8 Peripheral Multiplexer Select bit 2 8 1 P9 Peripheral Multiplexer Select bit 2 9 1 PMR21 Peripheral Mux Register 2 0x290 32 read-write n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 P1 Peripheral Multiplexer Select bit 2 1 1 P10 Peripheral Multiplexer Select bit 2 10 1 P11 Peripheral Multiplexer Select bit 2 11 1 P12 Peripheral Multiplexer Select bit 2 12 1 P13 Peripheral Multiplexer Select bit 2 13 1 P14 Peripheral Multiplexer Select bit 2 14 1 P15 Peripheral Multiplexer Select bit 2 15 1 P16 Peripheral Multiplexer Select bit 2 16 1 P17 Peripheral Multiplexer Select bit 2 17 1 P18 Peripheral Multiplexer Select bit 2 18 1 P19 Peripheral Multiplexer Select bit 2 19 1 P2 Peripheral Multiplexer Select bit 2 2 1 P20 Peripheral Multiplexer Select bit 2 20 1 P21 Peripheral Multiplexer Select bit 2 21 1 P22 Peripheral Multiplexer Select bit 2 22 1 P23 Peripheral Multiplexer Select bit 2 23 1 P24 Peripheral Multiplexer Select bit 2 24 1 P25 Peripheral Multiplexer Select bit 2 25 1 P26 Peripheral Multiplexer Select bit 2 26 1 P27 Peripheral Multiplexer Select bit 2 27 1 P28 Peripheral Multiplexer Select bit 2 28 1 P29 Peripheral Multiplexer Select bit 2 29 1 P3 Peripheral Multiplexer Select bit 2 3 1 P30 Peripheral Multiplexer Select bit 2 30 1 P31 Peripheral Multiplexer Select bit 2 31 1 P4 Peripheral Multiplexer Select bit 2 4 1 P5 Peripheral Multiplexer Select bit 2 5 1 P6 Peripheral Multiplexer Select bit 2 6 1 P7 Peripheral Multiplexer Select bit 2 7 1 P8 Peripheral Multiplexer Select bit 2 8 1 P9 Peripheral Multiplexer Select bit 2 9 1 PMR22 Peripheral Mux Register 2 0x6C0 32 read-write n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 P1 Peripheral Multiplexer Select bit 2 1 1 P10 Peripheral Multiplexer Select bit 2 10 1 P11 Peripheral Multiplexer Select bit 2 11 1 P12 Peripheral Multiplexer Select bit 2 12 1 P13 Peripheral Multiplexer Select bit 2 13 1 P14 Peripheral Multiplexer Select bit 2 14 1 P15 Peripheral Multiplexer Select bit 2 15 1 P16 Peripheral Multiplexer Select bit 2 16 1 P17 Peripheral Multiplexer Select bit 2 17 1 P18 Peripheral Multiplexer Select bit 2 18 1 P19 Peripheral Multiplexer Select bit 2 19 1 P2 Peripheral Multiplexer Select bit 2 2 1 P20 Peripheral Multiplexer Select bit 2 20 1 P21 Peripheral Multiplexer Select bit 2 21 1 P22 Peripheral Multiplexer Select bit 2 22 1 P23 Peripheral Multiplexer Select bit 2 23 1 P24 Peripheral Multiplexer Select bit 2 24 1 P25 Peripheral Multiplexer Select bit 2 25 1 P26 Peripheral Multiplexer Select bit 2 26 1 P27 Peripheral Multiplexer Select bit 2 27 1 P28 Peripheral Multiplexer Select bit 2 28 1 P29 Peripheral Multiplexer Select bit 2 29 1 P3 Peripheral Multiplexer Select bit 2 3 1 P30 Peripheral Multiplexer Select bit 2 30 1 P31 Peripheral Multiplexer Select bit 2 31 1 P4 Peripheral Multiplexer Select bit 2 4 1 P5 Peripheral Multiplexer Select bit 2 5 1 P6 Peripheral Multiplexer Select bit 2 6 1 P7 Peripheral Multiplexer Select bit 2 7 1 P8 Peripheral Multiplexer Select bit 2 8 1 P9 Peripheral Multiplexer Select bit 2 9 1 PMR2C0 Peripheral Mux Register 2 - Clear 0x70 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only PMR2C1 Peripheral Mux Register 2 - Clear 0x2A8 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only PMR2C2 Peripheral Mux Register 2 - Clear 0x6E0 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only PMR2S0 Peripheral Mux Register 2 - Set 0x68 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only PMR2S1 Peripheral Mux Register 2 - Set 0x29C 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only PMR2S2 Peripheral Mux Register 2 - Set 0x6D0 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only PMR2T0 Peripheral Mux Register 2 - Toggle 0x78 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only PMR2T1 Peripheral Mux Register 2 - Toggle 0x2B4 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only PMR2T2 Peripheral Mux Register 2 - Toggle 0x6F0 32 write-only n 0x0 0x0 P0 Peripheral Multiplexer Select bit 2 0 1 write-only P1 Peripheral Multiplexer Select bit 2 1 1 write-only P10 Peripheral Multiplexer Select bit 2 10 1 write-only P11 Peripheral Multiplexer Select bit 2 11 1 write-only P12 Peripheral Multiplexer Select bit 2 12 1 write-only P13 Peripheral Multiplexer Select bit 2 13 1 write-only P14 Peripheral Multiplexer Select bit 2 14 1 write-only P15 Peripheral Multiplexer Select bit 2 15 1 write-only P16 Peripheral Multiplexer Select bit 2 16 1 write-only P17 Peripheral Multiplexer Select bit 2 17 1 write-only P18 Peripheral Multiplexer Select bit 2 18 1 write-only P19 Peripheral Multiplexer Select bit 2 19 1 write-only P2 Peripheral Multiplexer Select bit 2 2 1 write-only P20 Peripheral Multiplexer Select bit 2 20 1 write-only P21 Peripheral Multiplexer Select bit 2 21 1 write-only P22 Peripheral Multiplexer Select bit 2 22 1 write-only P23 Peripheral Multiplexer Select bit 2 23 1 write-only P24 Peripheral Multiplexer Select bit 2 24 1 write-only P25 Peripheral Multiplexer Select bit 2 25 1 write-only P26 Peripheral Multiplexer Select bit 2 26 1 write-only P27 Peripheral Multiplexer Select bit 2 27 1 write-only P28 Peripheral Multiplexer Select bit 2 28 1 write-only P29 Peripheral Multiplexer Select bit 2 29 1 write-only P3 Peripheral Multiplexer Select bit 2 3 1 write-only P30 Peripheral Multiplexer Select bit 2 30 1 write-only P31 Peripheral Multiplexer Select bit 2 31 1 write-only P4 Peripheral Multiplexer Select bit 2 4 1 write-only P5 Peripheral Multiplexer Select bit 2 5 1 write-only P6 Peripheral Multiplexer Select bit 2 6 1 write-only P7 Peripheral Multiplexer Select bit 2 7 1 write-only P8 Peripheral Multiplexer Select bit 2 8 1 write-only P9 Peripheral Multiplexer Select bit 2 9 1 write-only PUER0 Pull-up Enable Register 0xE0 32 read-write n 0x0 0x0 P0 Pull-up Enable 0 1 P1 Pull-up Enable 1 1 P10 Pull-up Enable 10 1 P11 Pull-up Enable 11 1 P12 Pull-up Enable 12 1 P13 Pull-up Enable 13 1 P14 Pull-up Enable 14 1 P15 Pull-up Enable 15 1 P16 Pull-up Enable 16 1 P17 Pull-up Enable 17 1 P18 Pull-up Enable 18 1 P19 Pull-up Enable 19 1 P2 Pull-up Enable 2 1 P20 Pull-up Enable 20 1 P21 Pull-up Enable 21 1 P22 Pull-up Enable 22 1 P23 Pull-up Enable 23 1 P24 Pull-up Enable 24 1 P25 Pull-up Enable 25 1 P26 Pull-up Enable 26 1 P27 Pull-up Enable 27 1 P28 Pull-up Enable 28 1 P29 Pull-up Enable 29 1 P3 Pull-up Enable 3 1 P30 Pull-up Enable 30 1 P31 Pull-up Enable 31 1 P4 Pull-up Enable 4 1 P5 Pull-up Enable 5 1 P6 Pull-up Enable 6 1 P7 Pull-up Enable 7 1 P8 Pull-up Enable 8 1 P9 Pull-up Enable 9 1 PUER1 Pull-up Enable Register 0x350 32 read-write n 0x0 0x0 P0 Pull-up Enable 0 1 P1 Pull-up Enable 1 1 P10 Pull-up Enable 10 1 P11 Pull-up Enable 11 1 P12 Pull-up Enable 12 1 P13 Pull-up Enable 13 1 P14 Pull-up Enable 14 1 P15 Pull-up Enable 15 1 P16 Pull-up Enable 16 1 P17 Pull-up Enable 17 1 P18 Pull-up Enable 18 1 P19 Pull-up Enable 19 1 P2 Pull-up Enable 2 1 P20 Pull-up Enable 20 1 P21 Pull-up Enable 21 1 P22 Pull-up Enable 22 1 P23 Pull-up Enable 23 1 P24 Pull-up Enable 24 1 P25 Pull-up Enable 25 1 P26 Pull-up Enable 26 1 P27 Pull-up Enable 27 1 P28 Pull-up Enable 28 1 P29 Pull-up Enable 29 1 P3 Pull-up Enable 3 1 P30 Pull-up Enable 30 1 P31 Pull-up Enable 31 1 P4 Pull-up Enable 4 1 P5 Pull-up Enable 5 1 P6 Pull-up Enable 6 1 P7 Pull-up Enable 7 1 P8 Pull-up Enable 8 1 P9 Pull-up Enable 9 1 PUER2 Pull-up Enable Register 0x7C0 32 read-write n 0x0 0x0 P0 Pull-up Enable 0 1 P1 Pull-up Enable 1 1 P10 Pull-up Enable 10 1 P11 Pull-up Enable 11 1 P12 Pull-up Enable 12 1 P13 Pull-up Enable 13 1 P14 Pull-up Enable 14 1 P15 Pull-up Enable 15 1 P16 Pull-up Enable 16 1 P17 Pull-up Enable 17 1 P18 Pull-up Enable 18 1 P19 Pull-up Enable 19 1 P2 Pull-up Enable 2 1 P20 Pull-up Enable 20 1 P21 Pull-up Enable 21 1 P22 Pull-up Enable 22 1 P23 Pull-up Enable 23 1 P24 Pull-up Enable 24 1 P25 Pull-up Enable 25 1 P26 Pull-up Enable 26 1 P27 Pull-up Enable 27 1 P28 Pull-up Enable 28 1 P29 Pull-up Enable 29 1 P3 Pull-up Enable 3 1 P30 Pull-up Enable 30 1 P31 Pull-up Enable 31 1 P4 Pull-up Enable 4 1 P5 Pull-up Enable 5 1 P6 Pull-up Enable 6 1 P7 Pull-up Enable 7 1 P8 Pull-up Enable 8 1 P9 Pull-up Enable 9 1 PUERC0 Pull-up Enable Register - Clear 0xF0 32 write-only n 0x0 0x0 P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P2 Pull-up Enable 2 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P3 Pull-up Enable 3 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only PUERC1 Pull-up Enable Register - Clear 0x368 32 write-only n 0x0 0x0 P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P2 Pull-up Enable 2 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P3 Pull-up Enable 3 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only PUERC2 Pull-up Enable Register - Clear 0x7E0 32 write-only n 0x0 0x0 P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P2 Pull-up Enable 2 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P3 Pull-up Enable 3 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only PUERS0 Pull-up Enable Register - Set 0xE8 32 write-only n 0x0 0x0 P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P2 Pull-up Enable 2 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P3 Pull-up Enable 3 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only PUERS1 Pull-up Enable Register - Set 0x35C 32 write-only n 0x0 0x0 P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P2 Pull-up Enable 2 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P3 Pull-up Enable 3 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only PUERS2 Pull-up Enable Register - Set 0x7D0 32 write-only n 0x0 0x0 P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P2 Pull-up Enable 2 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P3 Pull-up Enable 3 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only PUERT0 Pull-up Enable Register - Toggle 0xF8 32 write-only n 0x0 0x0 P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P2 Pull-up Enable 2 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P3 Pull-up Enable 3 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only PUERT1 Pull-up Enable Register - Toggle 0x374 32 write-only n 0x0 0x0 P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P2 Pull-up Enable 2 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P3 Pull-up Enable 3 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only PUERT2 Pull-up Enable Register - Toggle 0x7F0 32 write-only n 0x0 0x0 P0 Pull-up Enable 0 1 write-only P1 Pull-up Enable 1 1 write-only P10 Pull-up Enable 10 1 write-only P11 Pull-up Enable 11 1 write-only P12 Pull-up Enable 12 1 write-only P13 Pull-up Enable 13 1 write-only P14 Pull-up Enable 14 1 write-only P15 Pull-up Enable 15 1 write-only P16 Pull-up Enable 16 1 write-only P17 Pull-up Enable 17 1 write-only P18 Pull-up Enable 18 1 write-only P19 Pull-up Enable 19 1 write-only P2 Pull-up Enable 2 1 write-only P20 Pull-up Enable 20 1 write-only P21 Pull-up Enable 21 1 write-only P22 Pull-up Enable 22 1 write-only P23 Pull-up Enable 23 1 write-only P24 Pull-up Enable 24 1 write-only P25 Pull-up Enable 25 1 write-only P26 Pull-up Enable 26 1 write-only P27 Pull-up Enable 27 1 write-only P28 Pull-up Enable 28 1 write-only P29 Pull-up Enable 29 1 write-only P3 Pull-up Enable 3 1 write-only P30 Pull-up Enable 30 1 write-only P31 Pull-up Enable 31 1 write-only P4 Pull-up Enable 4 1 write-only P5 Pull-up Enable 5 1 write-only P6 Pull-up Enable 6 1 write-only P7 Pull-up Enable 7 1 write-only P8 Pull-up Enable 8 1 write-only P9 Pull-up Enable 9 1 write-only PVR0 Pin Value Register 0xC0 32 read-only n 0x0 0x0 P0 Pin Value 0 1 read-only P1 Pin Value 1 1 read-only P10 Pin Value 10 1 read-only P11 Pin Value 11 1 read-only P12 Pin Value 12 1 read-only P13 Pin Value 13 1 read-only P14 Pin Value 14 1 read-only P15 Pin Value 15 1 read-only P16 Pin Value 16 1 read-only P17 Pin Value 17 1 read-only P18 Pin Value 18 1 read-only P19 Pin Value 19 1 read-only P2 Pin Value 2 1 read-only P20 Pin Value 20 1 read-only P21 Pin Value 21 1 read-only P22 Pin Value 22 1 read-only P23 Pin Value 23 1 read-only P24 Pin Value 24 1 read-only P25 Pin Value 25 1 read-only P26 Pin Value 26 1 read-only P27 Pin Value 27 1 read-only P28 Pin Value 28 1 read-only P29 Pin Value 29 1 read-only P3 Pin Value 3 1 read-only P30 Pin Value 30 1 read-only P31 Pin Value 31 1 read-only P4 Pin Value 4 1 read-only P5 Pin Value 5 1 read-only P6 Pin Value 6 1 read-only P7 Pin Value 7 1 read-only P8 Pin Value 8 1 read-only P9 Pin Value 9 1 read-only PVR1 Pin Value Register 0x320 32 read-only n 0x0 0x0 P0 Pin Value 0 1 read-only P1 Pin Value 1 1 read-only P10 Pin Value 10 1 read-only P11 Pin Value 11 1 read-only P12 Pin Value 12 1 read-only P13 Pin Value 13 1 read-only P14 Pin Value 14 1 read-only P15 Pin Value 15 1 read-only P16 Pin Value 16 1 read-only P17 Pin Value 17 1 read-only P18 Pin Value 18 1 read-only P19 Pin Value 19 1 read-only P2 Pin Value 2 1 read-only P20 Pin Value 20 1 read-only P21 Pin Value 21 1 read-only P22 Pin Value 22 1 read-only P23 Pin Value 23 1 read-only P24 Pin Value 24 1 read-only P25 Pin Value 25 1 read-only P26 Pin Value 26 1 read-only P27 Pin Value 27 1 read-only P28 Pin Value 28 1 read-only P29 Pin Value 29 1 read-only P3 Pin Value 3 1 read-only P30 Pin Value 30 1 read-only P31 Pin Value 31 1 read-only P4 Pin Value 4 1 read-only P5 Pin Value 5 1 read-only P6 Pin Value 6 1 read-only P7 Pin Value 7 1 read-only P8 Pin Value 8 1 read-only P9 Pin Value 9 1 read-only PVR2 Pin Value Register 0x780 32 read-only n 0x0 0x0 P0 Pin Value 0 1 read-only P1 Pin Value 1 1 read-only P10 Pin Value 10 1 read-only P11 Pin Value 11 1 read-only P12 Pin Value 12 1 read-only P13 Pin Value 13 1 read-only P14 Pin Value 14 1 read-only P15 Pin Value 15 1 read-only P16 Pin Value 16 1 read-only P17 Pin Value 17 1 read-only P18 Pin Value 18 1 read-only P19 Pin Value 19 1 read-only P2 Pin Value 2 1 read-only P20 Pin Value 20 1 read-only P21 Pin Value 21 1 read-only P22 Pin Value 22 1 read-only P23 Pin Value 23 1 read-only P24 Pin Value 24 1 read-only P25 Pin Value 25 1 read-only P26 Pin Value 26 1 read-only P27 Pin Value 27 1 read-only P28 Pin Value 28 1 read-only P29 Pin Value 29 1 read-only P3 Pin Value 3 1 read-only P30 Pin Value 30 1 read-only P31 Pin Value 31 1 read-only P4 Pin Value 4 1 read-only P5 Pin Value 5 1 read-only P6 Pin Value 6 1 read-only P7 Pin Value 7 1 read-only P8 Pin Value 8 1 read-only P9 Pin Value 9 1 read-only STER0 Schmitt Trigger Enable Register 0x2C0 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STER1 Schmitt Trigger Enable Register 0x620 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STER2 Schmitt Trigger Enable Register 0xB80 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STERC0 Schmitt Trigger Enable Register - Clear 0x2D0 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STERC1 Schmitt Trigger Enable Register - Clear 0x638 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STERC2 Schmitt Trigger Enable Register - Clear 0xBA0 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STERS0 Schmitt Trigger Enable Register - Set 0x2C8 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STERS1 Schmitt Trigger Enable Register - Set 0x62C 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STERS2 Schmitt Trigger Enable Register - Set 0xB90 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STERT0 Schmitt Trigger Enable Register - Toggle 0x2D8 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STERT1 Schmitt Trigger Enable Register - Toggle 0x644 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 STERT2 Schmitt Trigger Enable Register - Toggle 0xBB0 32 read-write n 0x0 0x0 P0 Schmitt Trigger Enable 0 1 P1 Schmitt Trigger Enable 1 1 P10 Schmitt Trigger Enable 10 1 P11 Schmitt Trigger Enable 11 1 P12 Schmitt Trigger Enable 12 1 P13 Schmitt Trigger Enable 13 1 P14 Schmitt Trigger Enable 14 1 P15 Schmitt Trigger Enable 15 1 P16 Schmitt Trigger Enable 16 1 P17 Schmitt Trigger Enable 17 1 P18 Schmitt Trigger Enable 18 1 P19 Schmitt Trigger Enable 19 1 P2 Schmitt Trigger Enable 2 1 P20 Schmitt Trigger Enable 20 1 P21 Schmitt Trigger Enable 21 1 P22 Schmitt Trigger Enable 22 1 P23 Schmitt Trigger Enable 23 1 P24 Schmitt Trigger Enable 24 1 P25 Schmitt Trigger Enable 25 1 P26 Schmitt Trigger Enable 26 1 P27 Schmitt Trigger Enable 27 1 P28 Schmitt Trigger Enable 28 1 P29 Schmitt Trigger Enable 29 1 P3 Schmitt Trigger Enable 3 1 P30 Schmitt Trigger Enable 30 1 P31 Schmitt Trigger Enable 31 1 P4 Schmitt Trigger Enable 4 1 P5 Schmitt Trigger Enable 5 1 P6 Schmitt Trigger Enable 6 1 P7 Schmitt Trigger Enable 7 1 P8 Schmitt Trigger Enable 8 1 P9 Schmitt Trigger Enable 9 1 UNLOCK0 Unlock Register 0x3C0 32 write-only n 0x0 0x0 ADDR Offset Register 0 10 write-only KEY Unlocking Key 24 8 UNLOCK1 Unlock Register 0x7A0 32 write-only n 0x0 0x0 ADDR Offset Register 0 10 write-only KEY Unlocking Key 24 8 UNLOCK2 Unlock Register 0xD80 32 write-only n 0x0 0x0 ADDR Offset Register 0 10 write-only KEY Unlocking Key 24 8 VERSION0 Version Register 0x3F8 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only VERSION1 Version Register 0x7F4 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only VERSION2 Version Register 0xDF0 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only HCACHE Cortex M I and D Cache Controller HCACHE 0x0 0x0 0x100 registers n CTRL Control Register 0x8 32 write-only n 0x0 0x0 CEN Cache Enable 0 1 write-only CENSelect NO Disable Cache Controller 0x0 YES Enable Cache Controller 0x1 MAINT0 Maintenance Register 0 0x20 32 write-only n 0x0 0x0 INVALL Cache Controller Invalidate All 0 1 write-only INVALLSelect NO No effect 0x0 YES Invalidate all cache entries 0x1 MAINT1 Maintenance Register 1 0x24 32 write-only n 0x0 0x0 INDEX Invalidate Index 4 4 write-only MCFG Monitor Configuration Register 0x28 32 read-write n 0x0 0x0 MODE Cache Controller Monitor Counter Mode 0 2 MODESelect CYCLE Cycle Counter 0x0 IHIT Instruction Hit Counter 0x1 DHIT Data Hit Counter 0x2 MCTRL Monitor Control Register 0x30 32 write-only n 0x0 0x0 SWRST Monitor Software Reset 0 1 write-only SWRSTSelect NO No effect 0x0 YES Reset event counter register 0x1 MEN Monitor Enable Register 0x2C 32 read-write n 0x0 0x0 MENABLE Monitor Enable 0 1 write-only MENABLESelect DIS Disable Monitor Counter 0x0 EN Enable Monitor Counter 0x1 MSR Monitor Status Register 0x34 32 read-only n 0x0 0x0 EVENTCNT Monitor Event Counter 0 32 read-only SR Status Register 0xC 32 read-write n 0x0 0x0 CSTS Cache Controller Status 0 1 read-only CSTSSelect DIS Cache Controller Disabled 0x0 EN Cache Controller Enabled 0x1 VERSION Version Register 0xFC 32 read-only n 0x0 0x0 MFN MFN 16 4 read-only VERSION VERSION 0 12 read-only HFLASHC Flash Controller FLASHCALW 0x0 0x0 0x400 registers n HFLASHC 0 FCMD Flash Controller Command Register 0x4 32 read-write n 0x0 0x0 CMD Command 0 6 CMDSelect NOP No Operation 0x0 WP Write Page 0x1 HSEN High Speed Mode Enable 0x10 HSDIS High Speed Mode Disable 0x11 EP Erase Page 0x2 CPB Clear Page Buffer 0x3 LP Lock Region containing page 0x4 UP Unlock Region containing page 0x5 EA Erase All, including secuity and fuse bits 0x6 WGPB Write General-Purpose fuse Bit 0x7 EGPB Erase General-Purpose fuse Bit 0x8 SSB Set Security Bit 0x9 PGPFB Program GPFuse Byte 0xa EAGPF Erase All GP Fuses 0xb QPR Quick Page Read 0xc WUP Write User Page 0xd EUP Erase User Page 0xe QPRUP Quick Page Read User Page 0xf KEY Write protection key 24 8 KEYSelect KEY 0xa5 PAGEN Page number 8 16 FCR Flash Controller Control Register 0x0 32 read-write n 0x0 0x0 FRDY Flash Ready Interrupt Enable 0 1 FRDYSelect 0 Flash Ready does not generate an interrupt 0x0 1 Flash Ready generates an interrupt 0x1 FWS Flash Wait State 6 1 FWSSelect 0 The flash is read with 0 wait states 0x0 1 The flash is read with 1 wait states 0x1 LOCKE Lock Error Interrupt Enable 2 1 LOCKESelect 0 Lock Error does not generate an interrupt 0x0 1 Lock Error generates an interrupt 0x1 PROGE Programming Error Interrupt Enable 3 1 PROGESelect 0 Programming Error does not generate an interrupt 0x0 1 Programming Error generates an interrupt 0x1 WS1OPT Wait State 1 Optimization 7 1 FGPFRHI Flash Controller General Purpose Fuse Register High 0x14 32 read-write n 0x0 0x0 GPF32 General Purpose Fuse 32 0 1 read-only GPF33 General Purpose Fuse 33 1 1 read-only GPF34 General Purpose Fuse 34 2 1 read-only GPF35 General Purpose Fuse 35 3 1 read-only GPF36 General Purpose Fuse 36 4 1 read-only GPF37 General Purpose Fuse 37 5 1 read-only GPF38 General Purpose Fuse 38 6 1 read-only GPF39 General Purpose Fuse 39 7 1 read-only GPF40 General Purpose Fuse 40 8 1 read-only GPF41 General Purpose Fuse 41 9 1 read-only GPF42 General Purpose Fuse 42 10 1 read-only GPF43 General Purpose Fuse 43 11 1 read-only GPF44 General Purpose Fuse 44 12 1 read-only GPF45 General Purpose Fuse 45 13 1 read-only GPF46 General Purpose Fuse 46 14 1 read-only GPF47 General Purpose Fuse 47 15 1 read-only GPF48 General Purpose Fuse 48 16 1 read-only GPF49 General Purpose Fuse 49 17 1 read-only GPF50 General Purpose Fuse 50 18 1 read-only GPF51 General Purpose Fuse 51 19 1 read-only GPF52 General Purpose Fuse 52 20 1 read-only GPF53 General Purpose Fuse 53 21 1 read-only GPF54 General Purpose Fuse 54 22 1 read-only GPF55 General Purpose Fuse 55 23 1 read-only GPF56 General Purpose Fuse 56 24 1 read-only GPF57 General Purpose Fuse 57 25 1 read-only GPF58 General Purpose Fuse 58 26 1 read-only GPF59 General Purpose Fuse 59 27 1 read-only GPF60 General Purpose Fuse 60 28 1 read-only GPF61 General Purpose Fuse 61 29 1 read-only GPF62 General Purpose Fuse 62 30 1 read-only GPF63 General Purpose Fuse 63 31 1 read-only FGPFRLO Flash Controller General Purpose Fuse Register Low 0x18 32 read-write n 0x0 0x0 GPF16 General Purpose Fuse 16 16 1 read-only GPF17 General Purpose Fuse 17 17 1 read-only GPF18 General Purpose Fuse 18 18 1 read-only GPF19 General Purpose Fuse 19 19 1 read-only GPF20 General Purpose Fuse 20 20 1 read-only GPF21 General Purpose Fuse 21 21 1 read-only GPF22 General Purpose Fuse 22 22 1 read-only GPF23 General Purpose Fuse 23 23 1 read-only GPF24 General Purpose Fuse 24 24 1 read-only GPF25 General Purpose Fuse 25 25 1 read-only GPF26 General Purpose Fuse 26 26 1 read-only GPF27 General Purpose Fuse 27 27 1 read-only GPF28 General Purpose Fuse 28 28 1 read-only GPF29 General Purpose Fuse 29 29 1 read-only GPF30 General Purpose Fuse 30 30 1 read-only GPF31 General Purpose Fuse 31 31 1 read-only LOCK0 Lock Bit 0 0 1 read-only LOCK1 Lock Bit 1 1 1 read-only LOCK10 Lock Bit 10 10 1 read-only LOCK11 Lock Bit 11 11 1 read-only LOCK12 Lock Bit 12 12 1 read-only LOCK13 Lock Bit 13 13 1 read-only LOCK14 Lock Bit 14 14 1 read-only LOCK15 Lock Bit 15 15 1 read-only LOCK2 Lock Bit 2 2 1 read-only LOCK3 Lock Bit 3 3 1 read-only LOCK4 Lock Bit 4 4 1 read-only LOCK5 Lock Bit 5 5 1 read-only LOCK6 Lock Bit 6 6 1 read-only LOCK7 Lock Bit 7 7 1 read-only LOCK8 Lock Bit 8 8 1 read-only LOCK9 Lock Bit 9 9 1 read-only FLASHCALW_FCMD Flash Controller Command Register 0x4 32 read-write n 0x0 0x0 CMD Command 0 6 CMDSelect NOP No Operation 0x0 WP Write Page 0x1 HSEN High Speed Mode Enable 0x10 HSDIS High Speed Mode Disable 0x11 EP Erase Page 0x2 CPB Clear Page Buffer 0x3 LP Lock Region containing page 0x4 UP Unlock Region containing page 0x5 EA Erase All, including secuity and fuse bits 0x6 WGPB Write General-Purpose fuse Bit 0x7 EGPB Erase General-Purpose fuse Bit 0x8 SSB Set Security Bit 0x9 PGPFB Program GPFuse Byte 0xa EAGPF Erase All GP Fuses 0xb QPR Quick Page Read 0xc WUP Write User Page 0xd EUP Erase User Page 0xe QPRUP Quick Page Read User Page 0xf KEY Write protection key 24 8 KEYSelect KEY None 0xa5 PAGEN Page number 8 16 FLASHCALW_FCR Flash Controller Control Register 0x0 32 read-write n 0x0 0x0 FRDY Flash Ready Interrupt Enable 0 1 FRDYSelect 0 Flash Ready does not generate an interrupt 0x0 1 Flash Ready generates an interrupt 0x1 FWS Flash Wait State 6 1 FWSSelect 0 The flash is read with 0 wait states 0x0 1 The flash is read with 1 wait states 0x1 LOCKE Lock Error Interrupt Enable 2 1 LOCKESelect 0 Lock Error does not generate an interrupt 0x0 1 Lock Error generates an interrupt 0x1 PROGE Programming Error Interrupt Enable 3 1 PROGESelect 0 Programming Error does not generate an interrupt 0x0 1 Programming Error generates an interrupt 0x1 WS1OPT Wait State 1 Optimization 7 1 FLASHCALW_FGPFRHI Flash Controller General Purpose Fuse Register High 0x14 32 read-write n 0x0 0x0 GPF32 General Purpose Fuse 32 0 1 read-only GPF33 General Purpose Fuse 33 1 1 read-only GPF34 General Purpose Fuse 34 2 1 read-only GPF35 General Purpose Fuse 35 3 1 read-only GPF36 General Purpose Fuse 36 4 1 read-only GPF37 General Purpose Fuse 37 5 1 read-only GPF38 General Purpose Fuse 38 6 1 read-only GPF39 General Purpose Fuse 39 7 1 read-only GPF40 General Purpose Fuse 40 8 1 read-only GPF41 General Purpose Fuse 41 9 1 read-only GPF42 General Purpose Fuse 42 10 1 read-only GPF43 General Purpose Fuse 43 11 1 read-only GPF44 General Purpose Fuse 44 12 1 read-only GPF45 General Purpose Fuse 45 13 1 read-only GPF46 General Purpose Fuse 46 14 1 read-only GPF47 General Purpose Fuse 47 15 1 read-only GPF48 General Purpose Fuse 48 16 1 read-only GPF49 General Purpose Fuse 49 17 1 read-only GPF50 General Purpose Fuse 50 18 1 read-only GPF51 General Purpose Fuse 51 19 1 read-only GPF52 General Purpose Fuse 52 20 1 read-only GPF53 General Purpose Fuse 53 21 1 read-only GPF54 General Purpose Fuse 54 22 1 read-only GPF55 General Purpose Fuse 55 23 1 read-only GPF56 General Purpose Fuse 56 24 1 read-only GPF57 General Purpose Fuse 57 25 1 read-only GPF58 General Purpose Fuse 58 26 1 read-only GPF59 General Purpose Fuse 59 27 1 read-only GPF60 General Purpose Fuse 60 28 1 read-only GPF61 General Purpose Fuse 61 29 1 read-only GPF62 General Purpose Fuse 62 30 1 read-only GPF63 General Purpose Fuse 63 31 1 read-only FLASHCALW_FGPFRLO Flash Controller General Purpose Fuse Register Low 0x18 32 read-write n 0x0 0x0 GPF16 General Purpose Fuse 16 16 1 read-only GPF17 General Purpose Fuse 17 17 1 read-only GPF18 General Purpose Fuse 18 18 1 read-only GPF19 General Purpose Fuse 19 19 1 read-only GPF20 General Purpose Fuse 20 20 1 read-only GPF21 General Purpose Fuse 21 21 1 read-only GPF22 General Purpose Fuse 22 22 1 read-only GPF23 General Purpose Fuse 23 23 1 read-only GPF24 General Purpose Fuse 24 24 1 read-only GPF25 General Purpose Fuse 25 25 1 read-only GPF26 General Purpose Fuse 26 26 1 read-only GPF27 General Purpose Fuse 27 27 1 read-only GPF28 General Purpose Fuse 28 28 1 read-only GPF29 General Purpose Fuse 29 29 1 read-only GPF30 General Purpose Fuse 30 30 1 read-only GPF31 General Purpose Fuse 31 31 1 read-only LOCK0 Lock Bit 0 0 1 read-only LOCK1 Lock Bit 1 1 1 read-only LOCK10 Lock Bit 10 10 1 read-only LOCK11 Lock Bit 11 11 1 read-only LOCK12 Lock Bit 12 12 1 read-only LOCK13 Lock Bit 13 13 1 read-only LOCK14 Lock Bit 14 14 1 read-only LOCK15 Lock Bit 15 15 1 read-only LOCK2 Lock Bit 2 2 1 read-only LOCK3 Lock Bit 3 3 1 read-only LOCK4 Lock Bit 4 4 1 read-only LOCK5 Lock Bit 5 5 1 read-only LOCK6 Lock Bit 6 6 1 read-only LOCK7 Lock Bit 7 7 1 read-only LOCK8 Lock Bit 8 8 1 read-only LOCK9 Lock Bit 9 9 1 read-only FLASHCALW_FPR Flash Controller Parameter Register 0xC 32 read-only n 0x0 0x0 FSZ Flash Size 0 4 read-only PSZ Page Size 8 3 read-only FLASHCALW_FSR Flash Controller Status Register 0x8 32 read-write n 0x0 0x0 ECCERR ECC Error Status 8 2 read-only ECCERRSelect NOERROR no error 0x0 ONEECCERR one ECC error detected 0x1 TWOECCERR two ECC errors detected 0x2 FRDY Flash Ready Status 0 1 read-only HSMODE High Speed Mode 6 1 read-only LOCK0 Lock Region 0 Lock Status 16 1 read-only LOCK1 Lock Region 1 Lock Status 17 1 read-only LOCK10 Lock Region 10 Lock Status 26 1 read-only LOCK11 Lock Region 11 Lock Status 27 1 read-only LOCK12 Lock Region 12 Lock Status 28 1 read-only LOCK13 Lock Region 13 Lock Status 29 1 read-only LOCK14 Lock Region 14 Lock Status 30 1 read-only LOCK15 Lock Region 15 Lock Status 31 1 read-only LOCK2 Lock Region 2 Lock Status 18 1 read-only LOCK3 Lock Region 3 Lock Status 19 1 read-only LOCK4 Lock Region 4 Lock Status 20 1 read-only LOCK5 Lock Region 5 Lock Status 21 1 read-only LOCK6 Lock Region 6 Lock Status 22 1 read-only LOCK7 Lock Region 7 Lock Status 23 1 read-only LOCK8 Lock Region 8 Lock Status 24 1 read-only LOCK9 Lock Region 9 Lock Status 25 1 read-only LOCKE Lock Error Status 2 1 read-only PROGE Programming Error Status 3 1 read-only QPRR Quick Page Read Result 5 1 read-only SECURITY Security Bit Status 4 1 read-only FLASHCALW_VERSION Flash Controller Version Register 0x10 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only FPR Flash Controller Parameter Register 0xC 32 read-only n 0x0 0x0 FSZ Flash Size 0 4 read-only PSZ Page Size 8 3 read-only FSR Flash Controller Status Register 0x8 32 read-write n 0x0 0x0 ECCERR ECC Error Status 8 2 read-only ECCERRSelect NOERROR no error 0x0 ONEECCERR one ECC error detected 0x1 TWOECCERR two ECC errors detected 0x2 FRDY Flash Ready Status 0 1 read-only HSMODE High Speed Mode 6 1 read-only LOCK0 Lock Region 0 Lock Status 16 1 read-only LOCK1 Lock Region 1 Lock Status 17 1 read-only LOCK10 Lock Region 10 Lock Status 26 1 read-only LOCK11 Lock Region 11 Lock Status 27 1 read-only LOCK12 Lock Region 12 Lock Status 28 1 read-only LOCK13 Lock Region 13 Lock Status 29 1 read-only LOCK14 Lock Region 14 Lock Status 30 1 read-only LOCK15 Lock Region 15 Lock Status 31 1 read-only LOCK2 Lock Region 2 Lock Status 18 1 read-only LOCK3 Lock Region 3 Lock Status 19 1 read-only LOCK4 Lock Region 4 Lock Status 20 1 read-only LOCK5 Lock Region 5 Lock Status 21 1 read-only LOCK6 Lock Region 6 Lock Status 22 1 read-only LOCK7 Lock Region 7 Lock Status 23 1 read-only LOCK8 Lock Region 8 Lock Status 24 1 read-only LOCK9 Lock Region 9 Lock Status 25 1 read-only LOCKE Lock Error Status 2 1 read-only PROGE Programming Error Status 3 1 read-only QPRR Quick Page Read Result 5 1 read-only SECURITY Security Bit Status 4 1 read-only VERSION Flash Controller Version Register 0x10 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only HMATRIX HSB Matrix HMATRIXB 0x0 0x0 0x400 registers n HMATRIXB_MCFG0 Master Configuration Register 0x0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG1 Master Configuration Register 0x4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG10 Master Configuration Register 0xDC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG11 Master Configuration Register 0x108 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG12 Master Configuration Register 0x138 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG13 Master Configuration Register 0x16C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG14 Master Configuration Register 0x1A4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG15 Master Configuration Register 0x1E0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG2 Master Configuration Register 0xC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG3 Master Configuration Register 0x18 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG4 Master Configuration Register 0x28 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG5 Master Configuration Register 0x3C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG6 Master Configuration Register 0x54 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG7 Master Configuration Register 0x70 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG8 Master Configuration Register 0x90 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG9 Master Configuration Register 0xB4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MRCR Master Remap Control Register 0x100 32 read-write n 0x0 0x0 RCB0 Remap Command bit for Master 0 0 1 RCB0Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB1 Remap Command bit for Master 1 1 1 RCB1Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB10 Remap Command bit for Master 10 10 1 RCB10Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB11 Remap Command bit for Master 11 11 1 RCB11Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB12 Remap Command bit for Master 12 12 1 RCB12Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB13 Remap Command bit for Master 13 13 1 RCB13Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB14 Remap Command bit for Master 14 14 1 RCB14Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB15 Remap Command bit for Master 15 15 1 RCB15Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB2 Remap Command bit for Master 2 2 1 RCB2Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB3 Remap Command bit for Master 3 3 1 RCB3Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB4 Remap Command bit for Master 4 4 1 RCB4Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB5 Remap Command bit for Master 5 5 1 RCB5Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB6 Remap Command bit for Master 6 6 1 RCB6Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB7 Remap Command bit for Master 7 7 1 RCB7Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB8 Remap Command bit for Master 8 8 1 RCB8Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB9 Remap Command bit for Master 9 9 1 RCB9Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 HMATRIXB_PRAS0 Priority Register A for Slave 0x100 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS1 Priority Register A for Slave 0x188 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS10 Priority Register A for Slave 0x7B8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS11 Priority Register A for Slave 0x890 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS12 Priority Register A for Slave 0x970 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS13 Priority Register A for Slave 0xA58 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS14 Priority Register A for Slave 0xB48 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS15 Priority Register A for Slave 0xC40 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS2 Priority Register A for Slave 0x218 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS3 Priority Register A for Slave 0x2B0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS4 Priority Register A for Slave 0x350 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS5 Priority Register A for Slave 0x3F8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS6 Priority Register A for Slave 0x4A8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS7 Priority Register A for Slave 0x560 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS8 Priority Register A for Slave 0x620 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS9 Priority Register A for Slave 0x6E8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRBS0 Priority Register B for Slave 0x108 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS1 Priority Register B for Slave 0x194 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS10 Priority Register B for Slave 0x7E8 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS11 Priority Register B for Slave 0x8C4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS12 Priority Register B for Slave 0x9A8 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS13 Priority Register B for Slave 0xA94 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS14 Priority Register B for Slave 0xB88 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS15 Priority Register B for Slave 0xC84 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS2 Priority Register B for Slave 0x228 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS3 Priority Register B for Slave 0x2C4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS4 Priority Register B for Slave 0x368 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS5 Priority Register B for Slave 0x414 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS6 Priority Register B for Slave 0x4C8 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS7 Priority Register B for Slave 0x584 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS8 Priority Register B for Slave 0x648 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS9 Priority Register B for Slave 0x714 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_SCFG0 Slave Configuration Register 0x80 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG1 Slave Configuration Register 0xC4 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG10 Slave Configuration Register 0x3DC 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG11 Slave Configuration Register 0x448 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG12 Slave Configuration Register 0x4B8 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG13 Slave Configuration Register 0x52C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG14 Slave Configuration Register 0x5A4 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG15 Slave Configuration Register 0x620 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG2 Slave Configuration Register 0x10C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG3 Slave Configuration Register 0x158 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG4 Slave Configuration Register 0x1A8 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG5 Slave Configuration Register 0x1FC 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG6 Slave Configuration Register 0x254 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG7 Slave Configuration Register 0x2B0 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG8 Slave Configuration Register 0x310 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG9 Slave Configuration Register 0x374 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SFR0 Special Function Register 0x220 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR1 Special Function Register 0x334 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR10 Special Function Register 0xD9C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR11 Special Function Register 0xED8 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR12 Special Function Register 0x1018 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR13 Special Function Register 0x115C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR14 Special Function Register 0x12A4 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR15 Special Function Register 0x13F0 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR2 Special Function Register 0x44C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR3 Special Function Register 0x568 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR4 Special Function Register 0x688 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR5 Special Function Register 0x7AC 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR6 Special Function Register 0x8D4 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR7 Special Function Register 0xA00 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR8 Special Function Register 0xB30 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR9 Special Function Register 0xC64 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 MCFG0 Master Configuration Register 0x0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG1 Master Configuration Register 0x4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG10 Master Configuration Register 0x28 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG11 Master Configuration Register 0x2C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG12 Master Configuration Register 0x30 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG13 Master Configuration Register 0x34 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG14 Master Configuration Register 0x38 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG15 Master Configuration Register 0x3C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG2 Master Configuration Register 0x8 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG3 Master Configuration Register 0xC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG4 Master Configuration Register 0x10 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG5 Master Configuration Register 0x14 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG6 Master Configuration Register 0x18 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG7 Master Configuration Register 0x1C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG8 Master Configuration Register 0x20 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MCFG9 Master Configuration Register 0x24 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 MRCR Master Remap Control Register 0x100 32 read-write n 0x0 0x0 RCB0 Remap Command bit for Master 0 0 1 RCB0Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB1 Remap Command bit for Master 1 1 1 RCB1Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB10 Remap Command bit for Master 10 10 1 RCB10Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB11 Remap Command bit for Master 11 11 1 RCB11Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB12 Remap Command bit for Master 12 12 1 RCB12Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB13 Remap Command bit for Master 13 13 1 RCB13Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB14 Remap Command bit for Master 14 14 1 RCB14Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB15 Remap Command bit for Master 15 15 1 RCB15Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB2 Remap Command bit for Master 2 2 1 RCB2Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB3 Remap Command bit for Master 3 3 1 RCB3Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB4 Remap Command bit for Master 4 4 1 RCB4Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB5 Remap Command bit for Master 5 5 1 RCB5Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB6 Remap Command bit for Master 6 6 1 RCB6Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB7 Remap Command bit for Master 7 7 1 RCB7Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB8 Remap Command bit for Master 8 8 1 RCB8Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 RCB9 Remap Command bit for Master 9 9 1 RCB9Select 0 Disable remapped address decoding for master 0x0 1 Enable remapped address decoding for master 0x1 PRAS0 Priority Register A for Slave 0x80 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS1 Priority Register A for Slave 0x88 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS10 Priority Register A for Slave 0xD0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS11 Priority Register A for Slave 0xD8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS12 Priority Register A for Slave 0xE0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS13 Priority Register A for Slave 0xE8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS14 Priority Register A for Slave 0xF0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS15 Priority Register A for Slave 0xF8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS2 Priority Register A for Slave 0x90 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS3 Priority Register A for Slave 0x98 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS4 Priority Register A for Slave 0xA0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS5 Priority Register A for Slave 0xA8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS6 Priority Register A for Slave 0xB0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS7 Priority Register A for Slave 0xB8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS8 Priority Register A for Slave 0xC0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS9 Priority Register A for Slave 0xC8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRBS0 Priority Register B for Slave 0x84 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS1 Priority Register B for Slave 0x8C 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS10 Priority Register B for Slave 0xD4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS11 Priority Register B for Slave 0xDC 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS12 Priority Register B for Slave 0xE4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS13 Priority Register B for Slave 0xEC 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS14 Priority Register B for Slave 0xF4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS15 Priority Register B for Slave 0xFC 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS2 Priority Register B for Slave 0x94 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS3 Priority Register B for Slave 0x9C 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS4 Priority Register B for Slave 0xA4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS5 Priority Register B for Slave 0xAC 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS6 Priority Register B for Slave 0xB4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS7 Priority Register B for Slave 0xBC 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS8 Priority Register B for Slave 0xC4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS9 Priority Register B for Slave 0xCC 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 SCFG0 Slave Configuration Register 0x40 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG1 Slave Configuration Register 0x44 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG10 Slave Configuration Register 0x68 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG11 Slave Configuration Register 0x6C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG12 Slave Configuration Register 0x70 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG13 Slave Configuration Register 0x74 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG14 Slave Configuration Register 0x78 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG15 Slave Configuration Register 0x7C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG2 Slave Configuration Register 0x48 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG3 Slave Configuration Register 0x4C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG4 Slave Configuration Register 0x50 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG5 Slave Configuration Register 0x54 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG6 Slave Configuration Register 0x58 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG7 Slave Configuration Register 0x5C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG8 Slave Configuration Register 0x60 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG9 Slave Configuration Register 0x64 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SFR0 Special Function Register 0x110 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR1 Special Function Register 0x114 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR10 Special Function Register 0x138 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR11 Special Function Register 0x13C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR12 Special Function Register 0x140 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR13 Special Function Register 0x144 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR14 Special Function Register 0x148 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR15 Special Function Register 0x14C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR2 Special Function Register 0x118 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR3 Special Function Register 0x11C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR4 Special Function Register 0x120 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR5 Special Function Register 0x124 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR6 Special Function Register 0x128 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR7 Special Function Register 0x12C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR8 Special Function Register 0x130 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR9 Special Function Register 0x134 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 IISC Inter-IC Sound (I2S) Controller IISC 0x0 0x0 0x400 registers n IISC 53 CR Control Register 0x0 32 write-only n 0x0 0x0 CKDIS Clocks Disable 3 1 CKDISSelect OFF No effect 0x0 ON Disables clocks 0x1 CKEN Clocks Enable 2 1 CKENSelect OFF No effect 0x0 ON Enables clocks if CKDIS is not set 0x1 RXDIS Receive Disable 1 1 RXDISSelect OFF No effect 0x0 ON Disables Data Receive 0x1 RXEN Receive Enable 0 1 RXENSelect OFF No effect 0x0 ON Enables Data Receive if RXDIS is not set 0x1 SWRST Software Reset 7 1 SWRSTSelect OFF No effect 0x0 ON Performs a software reset. Has priority on any other bit in CR 0x1 TXDIS Transmit Disable 5 1 TXDISSelect OFF No effect 0x0 ON Disables Data Transmit 0x1 TXEN Transmit Enable 4 1 TXENSelect OFF No effect 0x0 ON Enables Data Transmit if TXDIS is not set 0x1 IDR Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 RXOR Receive Overrun Interrupt Disable 2 1 RXORSelect OFF No effect 0x0 ON Disables the corresponding interrupt 0x1 RXRDY Receive Ready Interrupt Disable 1 1 RXRDYSelect OFF No effect 0x0 ON Disables the corresponding interrupt 0x1 TXRDY Transmit Ready Interrupt Disable 5 1 TXRDYSelect OFF No effect 0x0 ON Disables the corresponding interrupt 0x1 TXUR Transmit Underrun Interrupt Disable 6 1 TXURSelect OFF No effect 0x0 ON Disables the corresponding interrupt 0x1 IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 RXOR Receive Overrun Interrupt Enable 2 1 RXORSelect OFF No effect 0x0 ON Enables the corresponding interrupt 0x1 RXRDY Receiver Ready Interrupt Enable 1 1 RXRDYSelect OFF No effect 0x0 ON Enables the corresponding interrupt 0x1 TXRDY Transmit Ready Interrupt Enable 5 1 TXRDYSelect OFF No effect 0x0 ON Enables the corresponding interrupt 0x1 TXUR Transmit Underrun Interrupt Enable 6 1 TXURSelect OFF No effect 0x0 ON Enables the corresponding interrupt 0x1 IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 RXOR Receive Overrun Interrupt Mask 2 1 RXORSelect DISABLED The corresponding interrupt is disabled 0x0 ENABLED The corresponding interrupt is enabled 0x1 RXRDY Receive Ready Interrupt Mask 1 1 RXRDYSelect DISABLED The corresponding interrupt is disabled 0x0 ENABLED The corresponding interrupt is enabled 0x1 TXRDY Transmit Ready Interrupt Mask 5 1 TXRDYSelect DISABLED The corresponding interrupt is disabled 0x0 ENABLED The corresponding interrupt is enabled 0x1 TXUR Transmit Underrun Interrupt Mask 6 1 TXURSelect DISABLED The corresponding interrupt is disabled 0x0 ENABLED The corresponding interrupt is enabled 0x1 MR Mode Register 0x4 32 read-write n 0x0 0x0 DATALENGTH Data Word Length 2 3 DATALENGTHSelect 32 32 bits 0x0 24 24 bits 0x1 20 20 bits 0x2 18 18 bits 0x3 16 16 bits 0x4 16C 16 bits compact stereo 0x5 8 8 bits 0x6 8C 8 bits compact stereo 0x7 IMCKFS Master Clock to fs Ratio 24 6 IMCKFSSelect 16 16 fs 0x0 32 32 fs 0x1 384 384 fs 0x17 512 512 fs 0x1f 768 768 fs 0x2f 64 64 fs 0x3 1024 1024 fs 0x3f 128 128 fs 0x7 256 256 fs 0xf IMCKMODE Master Clock Mode 30 1 IMCKMODESelect NO_IMCK No IMCK generated 0x0 IMCK IMCK generated 0x1 IWS24 IWS Data Slot Width 31 1 IWS24Select 32 IWS Data Slot is 32-bit wide for DATALENGTH=18/20/24-bit 0x0 24 IWS Data Slot is 24-bit wide for DATALENGTH=18/20/24-bit 0x1 MODE Master/Slave/Controller Mode 0 1 MODESelect SLAVE Slave mode (only serial data handled, clocks received from external master or controller) 0x0 MASTER Master mode (clocks generated and output by IISC, serial data handled if CR.RXEN and/or CR.TXEN written to 1) 0x1 RXDMA Single or Multiple DMA Channels for Receiver 9 1 RXDMASelect SINGLE Single DMA channel 0x0 MULTIPLE One DMA channel per data channel 0x1 RXLOOP Loop-back Test Mode 10 1 RXLOOPSelect OFF Normal mode 0x0 ON ISDO internally connected to ISDI 0x1 RXMONO Receiver Mono 8 1 RXMONOSelect STEREO Normal mode 0x0 MONO Left channel data is duplicated to right channel 0x1 TXDMA Single or Multiple DMA Channels for Transmitter 13 1 TXDMASelect SINGLE Single DMA channel 0x0 MULTIPLE One DMA channel per data channel 0x1 TXMONO Transmitter Mono 12 1 TXMONOSelect STEREO Normal mode 0x0 MONO Left channel data is duplicated to right channel 0x1 TXSAME Transmit Data when Underrun 14 1 TXSAMESelect ZERO Zero data transmitted in case of underrun 0x0 SAME Last data transmitted in case of underrun 0x1 PARAMETER Parameter Register 0x2C 32 read-only n 0x0 0x0 FORMAT Data protocol format 7 1 FORMATSelect I2S I2S format, stereo with IWS low for left channel 0x0 NBCHAN Maximum number of channels - 1 16 5 RHR Receive Holding Register 0x20 32 read-only n 0x0 0x0 RDAT Receive Data 0 32 SCR Status Clear Register 0xC 32 write-only n 0x0 0x0 RXOR Receive Overrun 2 1 RXORSelect NO No effect 0x0 CLEAR Clears the corresponding SR bit 0x1 RXORCH Receive Overrun Channels 8 2 TXUR Transmit Underrun 6 1 TXURSelect NO No effect 0x0 CLEAR Clears the corresponding SR bit 0x1 TXURCH Transmit Underrun Channels 20 2 SR Status Register 0x8 32 read-only n 0x0 0x0 RXEN Receive Enable 0 1 RXENSelect OFF Receiver is effectively disabled, following a CR.RXDIS or CR.SWRST request 0x0 ON Receiver is effectively enabled, following a CR.RXEN request 0x1 RXOR Receive Overrun 2 1 RXORSelect NO No overrun 0x0 YES The previous received data has not been read. This data is lost 0x1 RXORCH Receive Overrun Channels 8 2 RXORCHSelect LEFT Overrun first occurred on left channel 0x0 RIGHT Overrun first occurred on right channel 0x1 RXRDY Receive Ready 1 1 RXRDYSelect EMPTY The register RHR is empty and can't be read 0x0 FULL The register RHR is full and is ready to be read 0x1 TXEN Transmit Enable 4 1 TXENSelect OFF Transmitter is effectively disabled, following a CR.TXDIS or CR.SWRST request 0x0 ON Transmitter is effectively enabled, following a CR.TXEN request 0x1 TXRDY Transmit Ready 5 1 TXRDYSelect FULL The register THR is full and can't be written 0x0 EMPTY The register THR is empty and is ready to be written 0x1 TXUR Transmit Underrun 6 1 TXURSelect NO No underrun 0x0 YES The last bit of the last data written to the register THR has been set. Until the next write to THR, data will be sent according to MR.TXSAME field 0x1 TXURCH Transmit Underrun Channels 20 2 TXURCHSelect LEFT Underrun first occurred on left channel 0x0 RIGHT Underrun first occurred on right channel 0x1 SSR Status Set Register 0x10 32 write-only n 0x0 0x0 RXOR Receive Overrun 2 1 RXORSelect NO No effect 0x0 SET Sets corresponding SR bit 0x1 RXORCH Receive Overrun Channels 8 2 TXUR Transmit Underrun 6 1 TXURSelect NO No effect 0x0 SET Sets corresponding SR bit 0x1 TXURCH Transmit Underrun Channels 20 2 THR Transmit Holding Register 0x24 32 write-only n 0x0 0x0 TDAT Transmit Data 0 32 VERSION Version Register 0x28 32 read-only n 0x0 0x0 VARIANT Reserved. Value subject to change. No functionality associated. 16 4 VERSION Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. 0 12 PARC Parallel Capture PARC 0x0 0x0 0x400 registers n PARC 74 CFG Configuration Register 0x0 32 read-write n 0x0 0x0 DSIZE Data Size 0 2 EDGE Sampling Edge Select 5 1 EMODE Events Mode 4 1 HALF Half Capture 6 1 ODD Odd Capture 7 1 SMODE Sampling Mode 2 2 CR Control Register 0x4 32 read-write n 0x0 0x0 DIS Disable 1 1 write-only EN Enable 0 1 START Start Capture 2 1 write-only STOP Stop Capture 3 1 ICR Interrupt Status Clear Register 0x18 32 write-only n 0x0 0x0 DRDY Data Ready Interrupt Status Clear 2 1 write-only OVR Overrun Interrupt Status Clear 3 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 DRDY Data Ready Interrupt Disable 2 1 write-only OVR Overrun Interrupt Disable 3 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 DRDY Data Ready Interrupt Enable 2 1 write-only OVR Overrun Interrupt Enable 3 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 DRDY Data Ready Interrupt Mask 2 1 read-only OVR Overrun Interrupt Mask 3 1 read-only RHR Receive Holding Register 0x1C 32 read-only n 0x0 0x0 CDATA Captured Data 0 32 read-only SR Status Register 0x14 32 read-only n 0x0 0x0 CS Capture Status 1 1 read-only DRDY Data Ready Interrupt Status 2 1 read-only EN Enable Status 0 1 read-only OVR Overrun Interrupt Status 3 1 read-only VERSION Version Register 0x20 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only PDCA Peripheral DMA Controller PDCA 0x0 0x0 0x1000 registers n PDCA_0 1 PDCA_1 2 PDCA_2 3 PDCA_3 4 PDCA_4 5 PDCA_5 6 PDCA_6 7 PDCA_7 8 PDCA_8 9 PDCA_9 10 PDCA_10 11 PDCA_11 12 PDCA_12 13 PDCA_13 14 PDCA_14 15 PDCA_15 16 CR0 Control Register 0x28 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR1 Control Register 0x7C 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR10 Control Register 0xEB0 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR11 Control Register 0x1184 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR12 Control Register 0x1498 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR13 Control Register 0x17EC 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR14 Control Register 0x1B80 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR15 Control Register 0x1F54 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR2 Control Register 0x110 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR3 Control Register 0x1E4 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR4 Control Register 0x2F8 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR5 Control Register 0x44C 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR6 Control Register 0x5E0 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR7 Control Register 0x7B4 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR8 Control Register 0x9C8 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 CR9 Control Register 0xC1C 32 write-only n 0x0 0x0 ECLR Error Clear 8 1 TDIS Transfer Disable 1 1 TEN Transfer Enable 0 1 IDR0 Interrupt Disable Register 0x48 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR1 Interrupt Disable Register 0xAC 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR10 Interrupt Disable Register 0xF70 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR11 Interrupt Disable Register 0x1254 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR12 Interrupt Disable Register 0x1578 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR13 Interrupt Disable Register 0x18DC 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR14 Interrupt Disable Register 0x1C80 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR15 Interrupt Disable Register 0x2064 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR2 Interrupt Disable Register 0x150 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR3 Interrupt Disable Register 0x234 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR4 Interrupt Disable Register 0x358 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR5 Interrupt Disable Register 0x4BC 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR6 Interrupt Disable Register 0x660 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR7 Interrupt Disable Register 0x844 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR8 Interrupt Disable Register 0xA68 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IDR9 Interrupt Disable Register 0xCCC 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER0 Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER1 Interrupt Enable Register 0xA0 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER10 Interrupt Enable Register 0xF40 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER11 Interrupt Enable Register 0x1220 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER12 Interrupt Enable Register 0x1540 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER13 Interrupt Enable Register 0x18A0 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER14 Interrupt Enable Register 0x1C40 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER15 Interrupt Enable Register 0x2020 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER2 Interrupt Enable Register 0x140 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER3 Interrupt Enable Register 0x220 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER4 Interrupt Enable Register 0x340 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER5 Interrupt Enable Register 0x4A0 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER6 Interrupt Enable Register 0x640 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER7 Interrupt Enable Register 0x820 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER8 Interrupt Enable Register 0xA40 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IER9 Interrupt Enable Register 0xCA0 32 write-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR0 Interrupt Mask Register 0x50 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR1 Interrupt Mask Register 0xB8 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR10 Interrupt Mask Register 0xFA0 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR11 Interrupt Mask Register 0x1288 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR12 Interrupt Mask Register 0x15B0 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR13 Interrupt Mask Register 0x1918 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR14 Interrupt Mask Register 0x1CC0 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR15 Interrupt Mask Register 0x20A8 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR2 Interrupt Mask Register 0x160 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR3 Interrupt Mask Register 0x248 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR4 Interrupt Mask Register 0x370 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR5 Interrupt Mask Register 0x4D8 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR6 Interrupt Mask Register 0x680 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR7 Interrupt Mask Register 0x868 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR8 Interrupt Mask Register 0xA90 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 IMR9 Interrupt Mask Register 0xCF8 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR0 Interrupt Status Register 0x58 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR1 Interrupt Status Register 0xC4 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR10 Interrupt Status Register 0xFD0 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR11 Interrupt Status Register 0x12BC 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR12 Interrupt Status Register 0x15E8 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR13 Interrupt Status Register 0x1954 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR14 Interrupt Status Register 0x1D00 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR15 Interrupt Status Register 0x20EC 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR2 Interrupt Status Register 0x170 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR3 Interrupt Status Register 0x25C 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR4 Interrupt Status Register 0x388 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR5 Interrupt Status Register 0x4F4 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR6 Interrupt Status Register 0x6A0 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR7 Interrupt Status Register 0x88C 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR8 Interrupt Status Register 0xAB8 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 ISR9 Interrupt Status Register 0xD24 32 read-only n 0x0 0x0 RCZ Reload Counter Zero 0 1 TERR Transfer Error 2 1 TRC Transfer Complete 1 1 MAR0 Memory Address Register 0x0 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR1 Memory Address Register 0x40 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR10 Memory Address Register 0xDC0 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR11 Memory Address Register 0x1080 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR12 Memory Address Register 0x1380 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR13 Memory Address Register 0x16C0 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR14 Memory Address Register 0x1A40 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR15 Memory Address Register 0x1E00 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR2 Memory Address Register 0xC0 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR3 Memory Address Register 0x180 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR4 Memory Address Register 0x280 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR5 Memory Address Register 0x3C0 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR6 Memory Address Register 0x540 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR7 Memory Address Register 0x700 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR8 Memory Address Register 0x900 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MAR9 Memory Address Register 0xB40 32 read-write n 0x0 0x0 MADDR Memory Address 0 32 MARR0 Memory Address Reload Register 0x18 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR1 Memory Address Reload Register 0x64 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR10 Memory Address Reload Register 0xE50 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR11 Memory Address Reload Register 0x111C 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR12 Memory Address Reload Register 0x1428 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR13 Memory Address Reload Register 0x1774 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR14 Memory Address Reload Register 0x1B00 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR15 Memory Address Reload Register 0x1ECC 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR2 Memory Address Reload Register 0xF0 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR3 Memory Address Reload Register 0x1BC 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR4 Memory Address Reload Register 0x2C8 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR5 Memory Address Reload Register 0x414 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR6 Memory Address Reload Register 0x5A0 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR7 Memory Address Reload Register 0x76C 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR8 Memory Address Reload Register 0x978 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MARR9 Memory Address Reload Register 0xBC4 32 read-write n 0x0 0x0 MARV Memory Address Reload Value 0 32 MR0 Mode Register 0x30 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR1 Mode Register 0x88 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR10 Mode Register 0xEE0 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR11 Mode Register 0x11B8 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR12 Mode Register 0x14D0 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR13 Mode Register 0x1828 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR14 Mode Register 0x1BC0 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR15 Mode Register 0x1F98 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR2 Mode Register 0x120 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR3 Mode Register 0x1F8 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR4 Mode Register 0x310 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR5 Mode Register 0x468 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR6 Mode Register 0x600 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR7 Mode Register 0x7D8 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR8 Mode Register 0x9F0 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 MR9 Mode Register 0xC48 32 read-write n 0x0 0x0 ETRIG Event trigger 2 1 RING Ring Buffer 3 1 SIZE Transfer size 0 2 SIZESelect Byte None 0x0 Half_Word None 0x1 Word None 0x2 PCONTROL Performance Control Register 0x800 32 read-write n 0x0 0x0 CH0EN Channel 0 Enabled 0 1 CH0OF Channel 0 Overflow Freeze 4 1 CH0RES Channel 0 counter reset 8 1 CH1EN Channel 1 Enabled. 1 1 CH1OF Channel 1 overflow freeze 5 1 CH1RES Channel 1 counter reset 9 1 MON0CH PDCA Channel to monitor with counter 0 16 6 MON1CH PDCA Channel to monitor with counter 1 24 6 PRDATA0 Channel 0 Read Data Cycles 0x804 32 read-only n 0x0 0x0 DATA Data Cycles Counted Since Last reset 0 32 PRDATA1 Channel 1 Read Data Cycles 0x81C 32 read-only n 0x0 0x0 DATA Data Cycles Counted Since Last reset 0 32 PRLAT0 Channel 0 Read Max Latency 0x80C 32 read-only n 0x0 0x0 LAT Maximum Transfer Initiation cycles counted since last reset 0 16 PRLAT1 Channel 1 Read Max Latency 0x824 32 read-only n 0x0 0x0 LAT Maximum Transfer initiation cycles counted since last reset 0 16 PRSTALL0 Channel 0 Read Stall Cycles 0x808 32 read-only n 0x0 0x0 STALL Stall Cycles counted since last reset 0 32 PRSTALL1 Channel Read Stall Cycles 0x820 32 read-only n 0x0 0x0 STALL Stall Cycles Counted since last reset 0 32 PSR0 Peripheral Select Register 0x8 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR1 Peripheral Select Register 0x4C 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR10 Peripheral Select Register 0xDF0 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR11 Peripheral Select Register 0x10B4 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR12 Peripheral Select Register 0x13B8 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR13 Peripheral Select Register 0x16FC 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR14 Peripheral Select Register 0x1A80 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR15 Peripheral Select Register 0x1E44 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR2 Peripheral Select Register 0xD0 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR3 Peripheral Select Register 0x194 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR4 Peripheral Select Register 0x298 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR5 Peripheral Select Register 0x3DC 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR6 Peripheral Select Register 0x560 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR7 Peripheral Select Register 0x724 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR8 Peripheral Select Register 0x928 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PSR9 Peripheral Select Register 0xB6C 32 read-write n 0x0 0x0 PID Peripheral Identifier 0 8 PWDATA0 Channel 0 Write Data Cycles 0x810 32 read-only n 0x0 0x0 DATA Data Cycles Counted since last Reset 0 32 PWDATA1 Channel 1 Write Data Cycles 0x828 32 read-only n 0x0 0x0 DATA Data cycles Counted Since last reset 0 32 PWLAT0 Channel0 Write Max Latency 0x818 32 read-only n 0x0 0x0 LAT Maximum transfer initiation cycles counted since last reset 0 16 PWLAT1 Channel 1 Read Max Latency 0x830 32 read-only n 0x0 0x0 LAT Maximum transfer initiation cycles counted since last reset 0 16 PWSTALL0 Channel 0 Write Stall Cycles 0x814 32 read-only n 0x0 0x0 STALL Stall cycles counted since last reset 0 32 PWSTALL1 Channel 1 Write stall Cycles 0x82C 32 read-only n 0x0 0x0 STALL Stall cycles counted since last reset 0 32 SR0 Status Register 0x38 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR1 Status Register 0x94 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR10 Status Register 0xF10 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR11 Status Register 0x11EC 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR12 Status Register 0x1508 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR13 Status Register 0x1864 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR14 Status Register 0x1C00 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR15 Status Register 0x1FDC 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR2 Status Register 0x130 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR3 Status Register 0x20C 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR4 Status Register 0x328 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR5 Status Register 0x484 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR6 Status Register 0x620 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR7 Status Register 0x7FC 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR8 Status Register 0xA18 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 SR9 Status Register 0xC74 32 read-only n 0x0 0x0 TEN Transfer Enabled 0 1 TCR0 Transfer Counter Register 0x10 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR1 Transfer Counter Register 0x58 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR10 Transfer Counter Register 0xE20 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR11 Transfer Counter Register 0x10E8 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR12 Transfer Counter Register 0x13F0 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR13 Transfer Counter Register 0x1738 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR14 Transfer Counter Register 0x1AC0 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR15 Transfer Counter Register 0x1E88 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR2 Transfer Counter Register 0xE0 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR3 Transfer Counter Register 0x1A8 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR4 Transfer Counter Register 0x2B0 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR5 Transfer Counter Register 0x3F8 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR6 Transfer Counter Register 0x580 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR7 Transfer Counter Register 0x748 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR8 Transfer Counter Register 0x950 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCR9 Transfer Counter Register 0xB98 32 read-write n 0x0 0x0 TCV Transfer Counter Value 0 16 TCRR0 Transfer Counter Reload Register 0x20 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR1 Transfer Counter Reload Register 0x70 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR10 Transfer Counter Reload Register 0xE80 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR11 Transfer Counter Reload Register 0x1150 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR12 Transfer Counter Reload Register 0x1460 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR13 Transfer Counter Reload Register 0x17B0 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR14 Transfer Counter Reload Register 0x1B40 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR15 Transfer Counter Reload Register 0x1F10 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR2 Transfer Counter Reload Register 0x100 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR3 Transfer Counter Reload Register 0x1D0 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR4 Transfer Counter Reload Register 0x2E0 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR5 Transfer Counter Reload Register 0x430 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR6 Transfer Counter Reload Register 0x5C0 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR7 Transfer Counter Reload Register 0x790 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR8 Transfer Counter Reload Register 0x9A0 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 TCRR9 Transfer Counter Reload Register 0xBF0 32 read-write n 0x0 0x0 TCRV Transfer Counter Reload Value 0 16 VERSION Version Register 0x834 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only PEVC Peripheral Event Controller PEVC 0x0 0x0 0x400 registers n PEVC_TR 19 PEVC_OV 20 BUSY Channel / User Busy 0x14 32 read-only n 0x0 0x0 BUSY Channel Status 0 32 BUSYSelect 0 No Action 0x0 1 Channel j or User j is Busy 0x1 CHDR Channel Disable Register 0x8 32 write-only n 0x0 0x0 CHD Channel Disable 0 32 CHDSelect 0 No Action 0x0 1 Disable Channel j 0x1 CHER Channel Enable Register 0x4 32 write-only n 0x0 0x0 CHE Channel Enable 0 32 CHESelect 0 No Action 0x0 1 Enable Channel j 0x1 CHMX0 Channel Multiplexer 0x200 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX1 Channel Multiplexer 0x304 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX10 Channel Multiplexer 0xCDC 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX11 Channel Multiplexer 0xE08 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX12 Channel Multiplexer 0xF38 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX13 Channel Multiplexer 0x106C 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX14 Channel Multiplexer 0x11A4 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX15 Channel Multiplexer 0x12E0 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX16 Channel Multiplexer 0x1420 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX17 Channel Multiplexer 0x1564 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX18 Channel Multiplexer 0x16AC 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX2 Channel Multiplexer 0x40C 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX3 Channel Multiplexer 0x518 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX4 Channel Multiplexer 0x628 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX5 Channel Multiplexer 0x73C 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX6 Channel Multiplexer 0x854 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX7 Channel Multiplexer 0x970 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX8 Channel Multiplexer 0xA90 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHMX9 Channel Multiplexer 0xBB4 32 read-write n 0x0 0x0 EVMX Event Multiplexer 0 6 EVMXSelect 0x00 Event 0 0x0 0x01 Event 1 0x1 SMX Software Event Multiplexer 8 1 SMXSelect 0 Hardware events 0x0 1 Software event 0x1 CHSR Channel Status Register 0x0 32 read-only n 0x0 0x0 CHS Channel Status 0 32 CHSSelect 0 Channel j Disabled 0x0 1 Channel j Enabled 0x1 EVS0 Event Shaper 0x400 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS1 Event Shaper 0x604 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS10 Event Shaper 0x18DC 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS11 Event Shaper 0x1B08 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS12 Event Shaper 0x1D38 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS13 Event Shaper 0x1F6C 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS14 Event Shaper 0x21A4 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS15 Event Shaper 0x23E0 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS16 Event Shaper 0x2620 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS17 Event Shaper 0x2864 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS18 Event Shaper 0x2AAC 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS19 Event Shaper 0x2CF8 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS2 Event Shaper 0x80C 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS20 Event Shaper 0x2F48 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS21 Event Shaper 0x319C 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS22 Event Shaper 0x33F4 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS23 Event Shaper 0x3650 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS24 Event Shaper 0x38B0 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS25 Event Shaper 0x3B14 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS26 Event Shaper 0x3D7C 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS27 Event Shaper 0x3FE8 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS28 Event Shaper 0x4258 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS29 Event Shaper 0x44CC 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS3 Event Shaper 0xA18 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS30 Event Shaper 0x4744 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS4 Event Shaper 0xC28 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS5 Event Shaper 0xE3C 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS6 Event Shaper 0x1054 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS7 Event Shaper 0x1270 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS8 Event Shaper 0x1490 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 EVS9 Event Shaper 0x16B4 32 read-write n 0x0 0x0 EN Event Shaper Enable 0 1 ENSelect 0 No Action 0x0 1 Event Shaper enable 0x1 IGFF Input Glitch Filter Fall 17 1 IGFFSelect 0 No Action 0x0 1 Input Glitch Filter : a falling edge on event input will raise trigger output 0x1 IGFON Input Glitch Filter Status 18 1 IGFR Input Glitch Filter Rise 16 1 IGFRSelect 0 No Action 0x0 1 Input Glitch Filter : a rising edge on event input will raise trigger output 0x1 IGFDR Input Glitch Filter Divider Register 0x300 32 read-write n 0x0 0x0 IGFDR Input Glitch Filter Divider Register 0 4 OVIDR Overrun Interrupt Mask Disable Register 0x44 32 write-only n 0x0 0x0 OVID Overrun Interrupt Disable 0 32 OVIDSelect 0 No Action 0x0 1 Enable Overrun Interrupt for Channel j 0x1 OVIER Overrun Interrupt Mask Enable Register 0x40 32 write-only n 0x0 0x0 OVIE Overrun Interrupt Enable 0 32 OVIESelect 0 No Action 0x0 1 Enable Overrun Interrupt for Channel j 0x1 OVIMR Overrun Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 OVIM Overrun Interrupt Mask 0 32 OVIMSelect 0 Overrun Interrupt for Channel j Disabled 0x0 1 Overrun Interrupt for Channel j Enabled 0x1 OVSCR Overrun Status Clear Register 0x54 32 write-only n 0x0 0x0 OVSC Overrun Interrupt Status Clear 0 32 OVSCSelect 0 No Action 0x0 1 Clear Overrun Status Bit j 0x1 OVSR Overrun Status Register 0x50 32 read-only n 0x0 0x0 OVS Overrun Interrupt Status 0 32 OVSSelect 0 No Overrun occured on Channel j 0x0 1 Overrun occured on Channel j 0x1 PARAMETER Parameter 0x3F8 32 read-only n 0x0 0x0 EVIN Number of Event Inputs / Generators 16 8 EVS_COUNT Number of Event Shapers 8 8 IGF_COUNT Number of Input Glitch Filters 0 8 TRIGOUT Number of Trigger Outputs / Channels / Users 24 8 SEV Software Event 0x10 32 write-only n 0x0 0x0 SEV Software Event 0 32 SEVSelect 0 No Action 0x0 1 CPU forces software event to channel j 0x1 TRIDR Trigger Interrupt Mask Disable Register 0x24 32 write-only n 0x0 0x0 TRID Trigger Interrupt Disable 0 32 TRIDSelect 0 No Action 0x0 1 Disable Trigger j Interrupt 0x1 TRIER Trigger Interrupt Mask Enable Register 0x20 32 write-only n 0x0 0x0 TRIE Trigger Interrupt Enable 0 32 TRIESelect 0 No Action 0x0 1 Enable Trigger j Interrupt 0x1 TRIMR Trigger Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 TRIM Trigger Interrupt Mask 0 32 TRIMSelect 0 Trigger j Interrupt Disabled 0x0 1 Trigger j Interrupt Enabled 0x1 TRSCR Trigger Status Clear Register 0x34 32 write-only n 0x0 0x0 TRSC Trigger Interrupt Status Clear 0 32 TRSCSelect 0 No Action 0x0 1 Clear TRSR[j] 0x1 TRSR Trigger Status Register 0x30 32 read-only n 0x0 0x0 TRS Trigger Interrupt Status 0 32 TRSSelect 0 Channel j did not send out an Event in the past 0x0 1 Channel j did send out an Event in the past 0x1 VERSION Version 0x3FC 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 VERSION Version Number 0 12 PICOUART Pico UART PICOUART 0x0 0x0 0x400 registers n CFG Configuration Register 0x4 32 read-write n 0x0 0x0 ACTION Action to perform 2 1 MATCH Data Match 8 8 SOURCE Source Enable Mode 0 2 CR Control Register 0x0 32 write-only n 0x0 0x0 DIS Disable 1 1 write-only EN Enable 0 1 RHR Receive Holding Register 0xC 32 read-only n 0x0 0x0 CDATA Received Data 0 32 read-only SR Status Register 0x8 32 read-only n 0x0 0x0 DRDY Data Ready Interrupt Status 1 1 read-only EN Enable Interrupt Status 0 1 read-only VERSION Version Register 0x20 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 read-only VERSION Version Number 0 12 read-only PM Power Manager PM 0x0 0x0 0x400 registers n PM 22 AWEN Asynchronous Wake Enable 0x188 32 read-write n 0x0 0x0 AWEN Asynchronous Wake Up 0 32 CFDCTRL Clock Failure Detector Control 0x54 32 read-write n 0x0 0x0 CFDEN Clock Failure Detection Enable 0 1 SFV Store Final Value 31 1 CONFIG Configuration Register 0x3F8 32 read-only n 0x0 0x0 HSBPEVC HSB PEVC Clock Implemented 7 1 PBA APBA Implemented 0 1 PBB APBB Implemented 1 1 PBC APBC Implemented 2 1 PBD APBD Implemented 3 1 CPUMASK CPU Mask 0x20 32 read-write n 0x0 0x0 OCD_ OCD CPU Clock Mask 0 1 CPUSEL CPU Clock Select 0x4 32 read-write n 0x0 0x0 CPUDIV CPU Division 7 1 CPUSEL CPU Clock Select 0 3 CPUSELSelect 0 fCPU:fmain. CPUDIV: 0x0 1 fCPU:fmain / 2^(CPUSEL+1) 0x1 FASTSLEEP Fast Sleep Register 0x194 32 read-write n 0x0 0x0 DFLL DFLL 24 1 FASTRCOSC RC80 or FLO 16 5 OSC Oscillator 0 1 PLL PLL 8 1 HSBMASK HSB Mask 0x24 32 read-write n 0x0 0x0 CRCCU_ CRCCU HSB Clock Mask 4 1 HFLASHC_ HFLASHC HSB Clock Mask 1 1 HRAMC1_ HRAMC1 HSB Clock Mask 2 1 HTOP0_ HTOP0 HSB Clock Mask 5 1 HTOP1_ HTOP1 HSB Clock Mask 6 1 HTOP2_ HTOP2 HSB Clock Mask 7 1 HTOP3_ HTOP3 HSB Clock Mask 8 1 PDCA_ PDCA HSB Clock Mask 0 1 USBC_ USBC HSB Clock Mask 3 1 ICR Interrupt Clear Register 0xD0 32 write-only n 0x0 0x0 AE Access Error Interrupt Status Clear 31 1 CFD Clock Failure Detected Interrupt Status Clear 0 1 CKRDY Clock Ready Interrupt Status Clear 5 1 WAKE Wake up Interrupt Status Clear 8 1 IDR Interrupt Disable Register 0xC4 32 write-only n 0x0 0x0 AE Access Error Interrupt Disable 31 1 CFD Clock Failure Detected Interrupt Disable 0 1 CKRDY Clock Ready Interrupt Disable 5 1 WAKE Wake up Interrupt Disable 8 1 WAKESelect 0 No effect 0x0 1 Disable Interrupt. 0x1 IER Interrupt Enable Register 0xC0 32 write-only n 0x0 0x0 AE Access Error Interrupt Enable 31 1 CFD Clock Failure Detected Interrupt Enable 0 1 CKRDY Clock Ready Interrupt Enable 5 1 WAKE Wake up Interrupt Enable 8 1 WAKESelect 0 No effect 0x0 1 Disable Interrupt. 0x1 IMR Interrupt Mask Register 0xC8 32 read-only n 0x0 0x0 AE Access Error Interrupt Mask 31 1 CFD Clock Failure Detected Interrupt Mask 0 1 CKRDY Clock Ready Interrupt Mask 5 1 WAKE Wake up Interrupt Mask 8 1 WAKESelect 0 No effect 0x0 1 Disable Interrupt. 0x1 ISR Interrupt Status Register 0xCC 32 read-only n 0x0 0x0 AE Access Error Interrupt Status 31 1 CFD Clock Failure Detected Interrupt Status 0 1 CKRDY Clock Ready Interrupt Status 5 1 WAKE Wake up Interrupt Status 8 1 WAKESelect 0 No effect 0x0 1 Disable Interrupt. 0x1 MCCTRL Main Clock Control 0x0 32 read-write n 0x0 0x0 MCSEL Main Clock Select 0 3 OBS Obsvervability 0x190 32 read-write n 0x0 0x0 PBADIVMASK PBA Divided Clock Mask 0x40 32 read-write n 0x0 0x0 PBAMASK PBA Mask 0x28 32 read-write n 0x0 0x0 ABDACB_ ABDACB APB Clock Enable 16 1 ACIFC_ ACIFC APB Clock Enable 14 1 ADCIFE_ ADCIFE APB Clock Enable 12 1 CATB_ CATB APB Clock Enable 19 1 DACC_ DACC APB Clock Enable 13 1 GLOC_ GLOC APB Clock Enable 15 1 IISC_ IISC APB Clock Enable 0 1 PARC_ PARC APB Clock Enable 18 1 SPI_ SPI APB Clock Enable 1 1 TC0_ TC0 APB Clock Enable 2 1 TC1_ TC1 APB Clock Enable 3 1 TRNG_ TRNG APB Clock Enable 17 1 TWIM0_ TWIM0 APB Clock Enable 4 1 TWIM1_ TWIM1 APB Clock Enable 6 1 TWIM2_ TWIM2 APB Clock Enable 21 1 TWIM3_ TWIM3 APB Clock Enable 22 1 TWIS0_ TWIS0 APB Clock Enable 5 1 TWIS1_ TWIS1 APB Clock Enable 7 1 USART0_ USART0 APB Clock Enable 8 1 USART1_ USART1 APB Clock Enable 9 1 USART2_ USART2 APB Clock Enable 10 1 USART3_ USART3 APB Clock Enable 11 1 PBASEL PBA Clock Select 0xC 32 read-write n 0x0 0x0 PBDIV PBA Division Select 7 1 PBSEL PBA Clock Select 0 3 PBBMASK PBB Mask 0x2C 32 read-write n 0x0 0x0 CRCCU_ CRCCU APB Clock Enable 4 1 HCACHE_ HCACHE APB Clock Enable 1 1 HFLASHC_ HFLASHC APB Clock Enable 0 1 HMATRIX_ HMATRIX APB Clock Enable 2 1 PDCA_ PDCA APB Clock Enable 3 1 PEVC_ PEVC APB Clock Enable 6 1 USBC_ USBC APB Clock Enable 5 1 PBBSEL PBB Clock Select 0x10 32 read-write n 0x0 0x0 PBDIV PBB Division Select 7 1 PBSEL PBB Clock Select 0 3 PBCMASK PBC Mask 0x30 32 read-write n 0x0 0x0 CHIPID_ CHIPID APB Clock Enable 1 1 FREQM_ FREQM APB Clock Enable 3 1 GPIO_ GPIO APB Clock Enable 4 1 PM_ PM APB Clock Enable 0 1 SCIF_ SCIF APB Clock Enable 2 1 PBCSEL PBC Clock Select 0x14 32 read-write n 0x0 0x0 PBDIV PBC Division Select 7 1 PBSEL PBC Clock Select 0 3 PBDMASK PBD Mask 0x34 32 read-write n 0x0 0x0 AST_ AST APB Clock Enable 2 1 BPM_ BPM APB Clock Enable 0 1 BSCIF_ BSCIF APB Clock Enable 1 1 EIC_ EIC APB Clock Enable 4 1 PICOUART_ PICOUART APB Clock Enable 5 1 WDT_ WDT APB Clock Enable 3 1 PBDSEL PBD Clock Select 0x18 32 read-write n 0x0 0x0 PBDIV PBD Division Select 7 1 PBSEL PBD Clock Select 0 3 PPCR Peripheral Power Control Register 0x160 32 read-write n 0x0 0x0 ACIFCRCMASK ACIFC Request Clock Mask 2 1 ADCIFERCMASK ADCIFE Request Clock Mask 7 1 ASTRCMASK AST Request Clock Mask 3 1 CATBRCMASK CAT Request Clock Mask 1 1 FWBGREF Flash Wait BGREF 9 1 FWBOD18 Flash Wait BOD18 10 1 PEVCRCMASK PEVC Request Clock Mask 6 1 RSTPUN Reset Pullup 0 1 TWIS0RCMASK TWIS0 Request Clock Mask 4 1 TWIS1RCMASK TWIS1 Request Clock Mask 5 1 VREGRCMASK VREG Request Clock Mask 8 1 RCAUSE Reset Cause Register 0x180 32 read-only n 0x0 0x0 BOD Brown-out Reset 1 1 BOD33 Brown-out 3.3V Reset 13 1 EXT External Reset Pin 2 1 OCDRST OCD Reset 8 1 POR Power-on Reset 0 1 POR33 Power-on Reset 10 1 WDT Watchdog Reset 3 1 SR Status Register 0xD4 32 read-only n 0x0 0x0 AE Access Error 31 1 CFD Clock Failure Detected 0 1 CKRDY Clock Ready 5 1 OCP Over Clock Detected 1 1 PERRDY Peripheral Ready 28 1 WAKE Wake up 8 1 WAKESelect 0 No effect 0x0 1 Disable Interrupt. 0x1 UNLOCK Unlock Register 0x58 32 write-only n 0x0 0x0 ADDR Unlock Address 0 10 KEY Unlock Key 24 8 VERSION Version Register 0x3FC 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 read-only VERSION Version number 0 12 read-only WCAUSE Wake Cause Register 0x184 32 read-only n 0x0 0x0 AST Asynchronous Timer 17 1 read-only BOD18_IRQ BOD18 Interrupt 4 1 read-only BOD33_IRQ BOD33 Interrupt 5 1 read-only EIC External Interrupt Controller 16 1 read-only LCDCA LCD Controller 7 1 read-only PICOUART Picopower UART 6 1 read-only PSOK Power Scaling OK 3 1 read-only TWI_SLAVE_0 Two-wire Slave Interface 0 0 1 read-only TWI_SLAVE_1 Two-wire Slave Interface 1 1 1 read-only USBC USB Device and Embedded Host Interface 2 1 read-only SCIF System Control Interface SCIF 0x0 0x0 0x400 registers n SCIF 23 CSCR Chip Specific Configuration Register 0x1C 32 read-write n 0x0 0x0 DFLL0CONF DFLL0 Config Register 0x28 32 read-write n 0x0 0x0 CALIB Calibration Value 24 4 CCDIS Chill Cycle Disable 5 1 EN Enable 0 1 FCD Fuse Calibration Done 23 1 LLAW Lose Lock After Wake 3 1 MODE Mode Selection 1 1 QLDIS Quick Lock Disable 6 1 RANGE Range Value 16 2 STABLE Stable DFLL Frequency 2 1 DFLL0MUL DFLL0 Multiplier Register 0x30 32 read-write n 0x0 0x0 MUL DFLL Multiply Factor 0 16 DFLL0RATIO DFLL0 Ratio Registe 0x3C 32 read-only n 0x0 0x0 RATIODIFF Multiplication Ratio Difference 0 16 read-only DFLL0SSG DFLL0 Spread Spectrum Generator Control Register 0x38 32 read-write n 0x0 0x0 AMPLITUDE SSG Amplitude 8 5 write-only EN Enable 0 1 write-only PRBS Pseudo Random Bit Sequence 1 1 write-only STEPSIZE SSG Step Size 16 5 write-only DFLL0STEP DFLL0 Step Register 0x34 32 read-write n 0x0 0x0 CSTEP Coarse Maximum Step 16 5 FSTEP Fine Maximum Step 0 8 DFLL0SYNC DFLL0 Synchronization Register 0x40 32 write-only n 0x0 0x0 SYNC Synchronization 0 1 write-only DFLL0VAL DFLL Value Register 0x2C 32 read-write n 0x0 0x0 COARSE Coarse Value 16 5 FINE Fine Value 0 8 DFLLIFBVERSION DFLL Version Register 0x3E8 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 FLOVERSION Frequency Locked Oscillator Version Register 0x3F0 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 FPCR Fractional Prescaler Control Register 0x68 32 read-write n 0x0 0x0 CKSEL Clock Input Selection 1 3 FPEN High Resolution Prescaler Enable 0 1 FPDIV Fractional Prescaler DIVIDER Register 0x70 32 read-write n 0x0 0x0 FPDIV Fractional Prescaler Division Factor 0 16 FPMUL Fractional Prescaler Multiplier Register 0x6C 32 read-write n 0x0 0x0 FPMUL Fractional Prescaler Multiplication Factor 0 16 GCCTRL0 Generic Clock Control 0xE8 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL1 Generic Clock Control 0x160 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL10 Generic Clock Control 0x64C 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL11 Generic Clock Control 0x6EC 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL2 Generic Clock Control 0x1DC 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL3 Generic Clock Control 0x25C 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL4 Generic Clock Control 0x2E0 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL5 Generic Clock Control 0x368 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL6 Generic Clock Control 0x3F4 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL7 Generic Clock Control 0x484 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL8 Generic Clock Control 0x518 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCCTRL9 Generic Clock Control 0x5B0 32 read-write n 0x0 0x0 CEN Clock Enable 0 1 DIV Division Factor 16 16 DIVEN Divide Enable 1 1 OSCSEL Clock Select 8 5 GCLKIFVERSION Generic Clock Version Register 0x3F8 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 GCLKPRESCVERSION Generic Clock Prescaler Version Register 0x3DC 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 HRPCR High Resolution Prescaler Control Register 0x64 32 read-write n 0x0 0x0 CKSEL Clock Input Selection 1 3 HRCOUNT High Resolution Counter 8 24 HRPEN High Resolution Prescaler Enable 0 1 ICR Interrupt Clear Register 0x10 32 write-only n 0x0 0x0 AE Access Error 31 1 write-only DFLL0LOCKC DFLL0 Lock Coarse 1 1 write-only DFLL0LOCKF DFLL0 Lock Fine 2 1 write-only DFLL0OOB DFLL0 Out Of Bounds 5 1 write-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 write-only DFLL0RDY DFLL0 Ready 3 1 write-only OSC0RDY OSC0 Ready 0 1 write-only PLL0LOCK PLL0 Lock 6 1 write-only PLL0LOCKLOST PLL0 Lock Lost 7 1 write-only RCFASTLOCK RCFAST Lock 13 1 write-only RCFASTLOCKLOST RCFAST Lock Lost 14 1 write-only IDR Interrupt Disable Register 0x4 32 write-only n 0x0 0x0 AE Access Error 31 1 write-only DFLL0LOCKC DFLL0 Lock Coarse 1 1 write-only DFLL0LOCKF DFLL0 Lock Fine 2 1 write-only DFLL0OOB DFLL0 Out Of Bounds 5 1 write-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 write-only DFLL0RDY DFLL0 Ready 3 1 write-only OSC0RDY OSC0 Ready 0 1 write-only PLL0LOCK PLL0 Lock 6 1 write-only PLL0LOCKLOST PLL0 Lock Lost 7 1 write-only RCFASTLOCK RCFAST Lock 13 1 write-only RCFASTLOCKLOST RCFAST Lock Lost 14 1 write-only IER Interrupt Enable Register 0x0 32 write-only n 0x0 0x0 AE Access Error 31 1 write-only DFLL0LOCKC DFLL0 Lock Coarse 1 1 write-only DFLL0LOCKF DFLL0 Lock Fine 2 1 write-only DFLL0OOB DFLL0 Out Of Bounds 5 1 write-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 write-only DFLL0RDY DFLL0 Ready 3 1 write-only OSC0RDY OSC0 Ready 0 1 write-only PLL0LOCK PLL0 Lock 6 1 write-only PLL0LOCKLOST PLL0 Lock Lost 7 1 write-only RCFASTLOCK RCFAST Lock 13 1 write-only RCFASTLOCKLOST RCFAST Lock Lost 14 1 write-only IMR Interrupt Mask Register 0x8 32 read-only n 0x0 0x0 AE Access Error 31 1 read-only DFLL0LOCKC DFLL0 Lock Coarse 1 1 read-only DFLL0LOCKF DFLL0 Lock Fine 2 1 read-only DFLL0OOB DFLL0 Out Of Bounds 5 1 read-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 read-only DFLL0RDY DFLL0 Ready 3 1 read-only OSC0RDY OSC0 Ready 0 1 read-only PLL0LOCK PLL0 Lock 6 1 read-only PLL0LOCKLOST PLL0 Lock Lost 7 1 read-only RCFASTLOCK RCFAST Lock 13 1 read-only RCFASTLOCKLOST RCFAST Lock Lost 14 1 read-only ISR Interrupt Status Register 0xC 32 read-only n 0x0 0x0 AE Access Error 31 1 read-only DFLL0LOCKC DFLL0 Lock Coarse 1 1 read-only DFLL0LOCKF DFLL0 Lock Fine 2 1 read-only DFLL0OOB DFLL0 Out Of Bounds 5 1 read-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 read-only DFLL0RDY DFLL0 Ready 3 1 read-only OSC0RDY OSC0 Ready 0 1 read-only PLL0LOCK PLL0 Lock 6 1 read-only PLL0LOCKLOST PLL0 Lock Lost 7 1 read-only RCFASTLOCK RCFAST Lock 13 1 read-only RCFASTLOCKLOST RCFAST Lock Lost 14 1 read-only OSCCTRL0 Oscillator Control Register 0x20 32 read-write n 0x0 0x0 AGC Automatic Gain Control 3 1 GAIN Gain 1 2 MODE Oscillator Mode 0 1 OSCEN Oscillator Enable 16 1 STARTUP Oscillator Start-up Time 8 4 OSCIFAVERSION Oscillator 0 Version Register 0x3E4 32 read-only n 0x0 0x0 VARIANT Variant nubmer 16 4 VERSION Version number 0 12 PCLKSR Power and Clocks Status Register 0x14 32 read-only n 0x0 0x0 DFLL0LOCKC DFLL0 Locked on Coarse Value 1 1 read-only DFLL0LOCKF DFLL0 Locked on Fine Value 2 1 read-only DFLL0OOB DFLL0 Track Out Of Bounds 5 1 read-only DFLL0RCS DFLL0 Reference Clock Stopped 4 1 read-only DFLL0RDY DFLL0 Synchronization Ready 3 1 read-only OSC0RDY OSC0 Ready 0 1 read-only PLL0LOCK PLL0 Locked on Accurate value 6 1 read-only PLL0LOCKLOST PLL0 lock lost value 7 1 read-only RCFASTLOCK RCFAST Locked on Accurate value 13 1 read-only RCFASTLOCKLOST RCFAST lock lost value 14 1 read-only PLL PLL0 Control Register 0x24 32 read-write n 0x0 0x0 PLLCOUNT PLL Count 24 6 PLLDIV PLL Division Factor 8 4 PLLEN PLL Enable 0 1 PLLMUL PLL Multiply Factor 16 4 PLLOPT PLL Option 3 3 PLLOSC PLL Oscillator Select 1 2 PLLIFAVERSION PLL Version Register 0x3E0 32 read-only n 0x0 0x0 VARIANT Variant nubmer 16 4 VERSION Version number 0 12 RC80MCR 80 MHz RC Oscillator Register 0x50 32 read-write n 0x0 0x0 CALIB Calibration Value 16 2 EN Enable 0 1 FCD Flash Calibration Done 7 1 RC80MVERSION 80MHz RC Oscillator Version Register 0x3F4 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 RCCR System RC Oscillator Calibration Register 0x44 32 read-write n 0x0 0x0 CALIB Calibration Value 0 10 FCD Flash Calibration Done 16 1 RCFASTCFG 4/8/12 MHz RC Oscillator Configuration Register 0x48 32 read-write n 0x0 0x0 CALIB Oscillator Calibration Value 16 7 EN Oscillator Enable 0 1 FCD RCFAST Fuse Calibration Done 7 1 FRANGE Frequency Range 8 2 JITMODE Jitter Mode 2 1 LOCKMARGIN Accepted Count Error for Lock 12 4 NBPERIODS Number of 32kHz Periods 4 3 TUNEEN Tuner Enable 1 1 RCFASTSR 4/8/12 MHz RC Oscillator Status Register 0x4C 32 read-write n 0x0 0x0 CNTERR Current Count Error 16 5 CURTRIM Current Trim Value 0 7 LOCK Lock 24 1 LOCKLOST Lock Lost 25 1 SIGN Sign of Current Count Error 21 1 UPDATED Current Trim Value Updated 31 1 RCFASTVERSION 4/8/12 MHz RC Oscillator Version Register 0x3D8 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 RCOSCIFAVERSION System RC Oscillator Version Register 0x3EC 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 UNLOCK Unlock Register 0x18 32 write-only n 0x0 0x0 ADDR Unlock Address 0 10 write-only KEY Unlock Key 24 8 write-only VERSION SCIF Version Register 0x3FC 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 SMAP System Manager Access Port SMAP 0x0 0x0 0x400 registers n ADDR Address Register 0xC 32 read-write n 0x0 0x0 ADDR Address Value 2 30 CIDR Chip ID Register 0xF0 32 read-only n 0x0 0x0 ARCH Architecture Identifier 21 7 read-only EPROC Embedded Processor 5 3 read-only EXT Extension Flag 31 1 read-only NVPSIZ Nonvolatile Program Memory Size 8 4 read-only NVPSIZ2 Second Nonvolatile Program Memory Size 12 4 read-only NVPTYP Nonvolatile Program Memory Type 28 3 read-only SRAMSIZ Internal SRAM Size 16 5 read-only VERSION Version of the Device 0 5 read-only CR Control Register 0x0 32 write-only n 0x0 0x0 CE Chip Erase 4 1 write-only CRC User Page Read 2 1 write-only DIS Disable 1 1 write-only EN Enable 0 1 write-only FSPR Flash Supplementary Page Read 3 1 write-only DATA Data Register 0x14 32 read-write n 0x0 0x0 DATA Generic data register 0 32 EXID Chip ID Extension Register 0xF4 32 read-only n 0x0 0x0 EXID Chip ID Extension 0 32 read-only IDR AP Identification register 0xFC 32 read-only n 0x0 0x0 APID AP Identification 4 4 read-only APIDV AP Identification Variant 0 4 read-only CC JEP-106 Continuation Code 24 4 read-only CLSS Class 16 1 read-only IC JEP-106 Identity Code 17 7 read-only REVISION Revision 28 4 read-only LENGTH Length Register 0x10 32 read-write n 0x0 0x0 LENGTH Length Register 2 30 SCR Status Clear Register 0x8 32 write-only n 0x0 0x0 BERR Bus error 2 1 write-only DONE Done 0 1 write-only FAIL Failure 3 1 write-only HCR Hold Core Register 1 1 write-only LCK Lock error 4 1 write-only SR Status Register 0x4 32 read-only n 0x0 0x0 BERR Bus error 2 1 read-only DBGP Debugger Present 10 1 read-only DONE Operation done 0 1 read-only EN Enabled 8 1 read-only FAIL Failure 3 1 read-only HCR Hold Core reset 1 1 read-only LCK Lock 4 1 read-only PROT Protected 9 1 read-only STATE State 24 3 read-only VERSION VERSION register 0x28 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 read-only VERSION Version number 0 12 read-only SPI Serial Peripheral Interface SPI 0x0 0x0 0x400 registers n SPI 54 CR Control Register 0x0 32 write-only n 0x0 0x0 FLUSHFIFO Flush FIFO command 8 1 LASTXFER Last Transfer 24 1 LASTXFERSelect 0 No effect. 0x0 1 The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, thisallows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TDtransfer has completed. 0x1 SPIDIS SPI Disable 1 1 SPIDISSelect 0 No effect. 0x0 1 Disables the SPI.All pins are set in input mode and no data is received or transmitted.If a transfer is in progress, the transfer is finished before the SPI is disabled.If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. 0x1 SPIEN SPI Enable 0 1 SPIENSelect 0 No effect. 0x0 1 Enables the SPI to transfer and receive data. 0x1 SWRST SPI Software Reset 7 1 SWRSTSelect 0 No effect. 0x0 1 Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. 0x1 CSR0 Chip Select Register 0x60 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 BITSSelect 8_BPT 8 bits per transfer 0x0 9_BPT 9 bits per transfer 0x1 10_BPT 10 bits per transfer 0x2 11_BPT 11 bits per transfer 0x3 12_BPT 12 bits per transfer 0x4 13_BPT 13 bits per transfer 0x5 14_BPT 14 bits per transfer 0x6 15_BPT 15 bits per transfer 0x7 16_BPT 16 bits per transfer 0x8 CPOL Clock Polarity 0 1 CPOLSelect 0 The inactive state value of SPCK is logic level zero. 0x0 1 The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices. 0x1 CSAAT Chip Select Active After Transfer 3 1 CSAATSelect 0 The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 0x0 1 The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select. 0x1 CSNAAT Chip Select Not Active After Transfer 2 1 DLYBCT Delay Between Consecutive Transfers 24 8 DLYBS Delay Before SPCK 16 8 NCPHA Clock Phase 1 1 NCPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices. 0x1 SCBR Serial Clock Baud Rate 8 8 CSR1 Chip Select Register 0x94 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 BITSSelect 8_BPT 8 bits per transfer 0x0 9_BPT 9 bits per transfer 0x1 10_BPT 10 bits per transfer 0x2 11_BPT 11 bits per transfer 0x3 12_BPT 12 bits per transfer 0x4 13_BPT 13 bits per transfer 0x5 14_BPT 14 bits per transfer 0x6 15_BPT 15 bits per transfer 0x7 16_BPT 16 bits per transfer 0x8 CPOL Clock Polarity 0 1 CPOLSelect 0 The inactive state value of SPCK is logic level zero. 0x0 1 The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices. 0x1 CSAAT Chip Select Active After Transfer 3 1 CSAATSelect 0 The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 0x0 1 The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select. 0x1 CSNAAT Chip Select Not Active After Transfer 2 1 DLYBCT Delay Between Consecutive Transfers 24 8 DLYBS Delay Before SPCK 16 8 NCPHA Clock Phase 1 1 NCPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices. 0x1 SCBR Serial Clock Baud Rate 8 8 CSR2 Chip Select Register 0xCC 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 BITSSelect 8_BPT 8 bits per transfer 0x0 9_BPT 9 bits per transfer 0x1 10_BPT 10 bits per transfer 0x2 11_BPT 11 bits per transfer 0x3 12_BPT 12 bits per transfer 0x4 13_BPT 13 bits per transfer 0x5 14_BPT 14 bits per transfer 0x6 15_BPT 15 bits per transfer 0x7 16_BPT 16 bits per transfer 0x8 CPOL Clock Polarity 0 1 CPOLSelect 0 The inactive state value of SPCK is logic level zero. 0x0 1 The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices. 0x1 CSAAT Chip Select Active After Transfer 3 1 CSAATSelect 0 The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 0x0 1 The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select. 0x1 CSNAAT Chip Select Not Active After Transfer 2 1 DLYBCT Delay Between Consecutive Transfers 24 8 DLYBS Delay Before SPCK 16 8 NCPHA Clock Phase 1 1 NCPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices. 0x1 SCBR Serial Clock Baud Rate 8 8 CSR3 Chip Select Register 0x108 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 BITSSelect 8_BPT 8 bits per transfer 0x0 9_BPT 9 bits per transfer 0x1 10_BPT 10 bits per transfer 0x2 11_BPT 11 bits per transfer 0x3 12_BPT 12 bits per transfer 0x4 13_BPT 13 bits per transfer 0x5 14_BPT 14 bits per transfer 0x6 15_BPT 15 bits per transfer 0x7 16_BPT 16 bits per transfer 0x8 CPOL Clock Polarity 0 1 CPOLSelect 0 The inactive state value of SPCK is logic level zero. 0x0 1 The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices. 0x1 CSAAT Chip Select Active After Transfer 3 1 CSAATSelect 0 The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 0x0 1 The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select. 0x1 CSNAAT Chip Select Not Active After Transfer 2 1 DLYBCT Delay Between Consecutive Transfers 24 8 DLYBS Delay Before SPCK 16 8 NCPHA Clock Phase 1 1 NCPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices. 0x1 SCBR Serial Clock Baud Rate 8 8 FEATURES Features Register 0xF8 32 read-only n 0x0 0x0 BRPBHSB Bridge Type is PB to HSB 18 1 CSNAATIMPL CSNAAT Features are Implemented 17 1 EXTDEC External Decoder is True 16 1 FIFORIMPL FIFO in Reception is Implemented 19 1 LENCONF Character Length is Configurable 8 1 LENNCONF Character Length if not Configurable 9 7 NCS Number of Chip Selects 0 4 PCONF Polarity is Configurable 4 1 PHCONF Phase is Configurable 6 1 PHZNCONF Phase is Zero if Phase is not Configurable 7 1 PPNCONF Polarity is Positive if Polarity is not Configurable 5 1 SWPIMPL Spurious Write Protection is Implemented 20 1 IDR Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 ENDRX End of Receive Buffer Interrupt Disable 4 1 ENDRXSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 ENDTX End of Transmit Buffer Interrupt Disable 5 1 ENDTXSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 MODF Mode Fault Error Interrupt Disable 2 1 MODFSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 NSSR NSS Rising Interrupt Disable 8 1 NSSRSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 OVRES Overrun Error Interrupt Disable 3 1 OVRESSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 RDRF Receive Data Register Full Interrupt Disable 0 1 RDRFSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 RXBUFF Receive Buffer Full Interrupt Disable 6 1 RXBUFFSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 TDRE Transmit Data Register Empty Interrupt Disable 1 1 TDRESelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 TXBUFE Transmit Buffer Empty Interrupt Disable 7 1 TXBUFESelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 TXEMPTY Transmission Registers Empty Disable 9 1 TXEMPTYSelect 0 No effect. 0x0 1 Disables the corresponding interrupt. 0x1 UNDES Underrun Error Interrupt Disable 10 1 IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 ENDRX End of Receive Buffer Interrupt Enable 4 1 ENDRXSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 ENDTX End of Transmit Buffer Interrupt Enable 5 1 ENDTXSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 MODF Mode Fault Error Interrupt Enable 2 1 MODFSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 NSSR NSS Rising Interrupt Enable 8 1 NSSRSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 OVRES Overrun Error Interrupt Enable 3 1 OVRESSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 RDRF Receive Data Register Full Interrupt Enable 0 1 RDRFSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 RXBUFF Receive Buffer Full Interrupt Enable 6 1 RXBUFFSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 TDRE Transmit Data Register Empty Interrupt Enable 1 1 TDRESelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 TXBUFE Transmit Buffer Empty Interrupt Enable 7 1 TXBUFESelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 TXEMPTY Transmission Registers Empty Enable 9 1 TXEMPTYSelect 0 No effect. 0x0 1 Enables the corresponding interrupt. 0x1 UNDES Underrun Error Interrupt Enable 10 1 IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 ENDRX End of Receive Buffer Interrupt Mask 4 1 ENDRXSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 ENDTX End of Transmit Buffer Interrupt Mask 5 1 ENDTXSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 MODF Mode Fault Error Interrupt Mask 2 1 MODFSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 NSSR NSS Rising Interrupt Mask 8 1 NSSRSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 OVRES Overrun Error Interrupt Mask 3 1 OVRESSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 RDRF Receive Data Register Full Interrupt Mask 0 1 RDRFSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 RXBUFF Receive Buffer Full Interrupt Mask 6 1 RXBUFFSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 TDRE Transmit Data Register Empty Interrupt Mask 1 1 TDRESelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 TXBUFE Transmit Buffer Empty Interrupt Mask 7 1 TXBUFESelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 TXEMPTY Transmission Registers Empty Mask 9 1 TXEMPTYSelect 0 The corresponding interrupt is not enabled. 0x0 1 The corresponding interrupt is enabled. 0x1 UNDES Underrun Error Interrupt Mask 10 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 DLYBCS Delay Between Chip Selects 24 8 LLB Local Loopback Enable 7 1 LLBSelect 0 Local loopback path disabled. 0x0 1 Local loopback path enabled.LLB controls the local loopback on the data serializer for testing in Master Mode only. 0x1 MODFDIS Mode Fault Detection 4 1 MODFDISSelect 0 Mode fault detection is enabled. 0x0 1 Mode fault detection is disabled. 0x1 MSTR Master/Slave Mode 0 1 MSTRSelect 0 SPI is in Slave mode. 0x0 1 SPI is in Master mode. 0x1 PCS Peripheral Chip Select 16 4 PCSDEC Chip Select Decode 2 1 PCSDECSelect 0 The chip selects are directly connected to a peripheral device. 0x0 1 The four chip select lines are connected to a 4- to 16-bit decoder.When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bitdecoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:CSR0 defines peripheral chip select signals 0 to 3.CSR1 defines peripheral chip select signals 4 to 7.CSR2 defines peripheral chip select signals 8 to 11.CSR3 defines peripheral chip select signals 12 to 15. 0x1 PS Peripheral Select 1 1 PSSelect 0 Fixed Peripheral Select. 0x0 1 Variable Peripheral Select. 0x1 RXFIFOEN FIFO in Reception Enable 6 1 WDRBT wait data read before transfer 5 1 RDR Receive Data Register 0x8 32 read-only n 0x0 0x0 PCS Peripheral Chip Select 16 4 RD Receive Data 0 16 SR Status Register 0x10 32 read-only n 0x0 0x0 ENDRX End of RX buffer 4 1 ENDRXSelect 0 The Receive Counter Register has not reached 0 since the last write in RCR or RNCR. 0x0 1 The Receive Counter Register has reached 0 since the last write in RCR or RNCR. 0x1 ENDTX End of TX buffer 5 1 ENDTXSelect 0 The Transmit Counter Register has not reached 0 since the last write in TCR or TNCR. 0x0 1 The Transmit Counter Register has reached 0 since the last write in TCR or TNCR. 0x1 MODF Mode Fault Error 2 1 MODFSelect 0 No Mode Fault has been detected since the last read of SR. 0x0 1 A Mode Fault occurred since the last read of the SR. 0x1 NSSR NSS Rising 8 1 NSSRSelect 0 No rising edge detected on NSS pin since last read. 0x0 1 A rising edge occurred on NSS pin since last read. 0x1 OVRES Overrun Error Status 3 1 OVRESSelect 0 No overrun has been detected since the last read of SR. 0x0 1 An overrun has occurred since the last read of SR. 0x1 RDRF Receive Data Register Full 0 1 RDRFSelect 0 No data has been received since the last read of RDR 0x0 1 Data has been received and the received data has been transferred from the serializer to RDR since the last readof RDR. 0x1 RXBUFF RX Buffer Full 6 1 RXBUFFSelect 0 RCR or RNCR has a value other than 0. 0x0 1 Both RCR and RNCR has a value of 0. 0x1 SPIENS SPI Enable Status 16 1 SPIENSSelect 0 SPI is disabled. 0x0 1 SPI is enabled. 0x1 TDRE Transmit Data Register Empty 1 1 TDRESelect 0 Data has been written to TDR and not yet transferred to the serializer. 0x0 1 The last data written in the Transmit Data Register has been transferred to the serializer.TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. 0x1 TXBUFE TX Buffer Empty 7 1 TXBUFESelect 0 TCR or TNCR has a value other than 0. 0x0 1 Both TCR and TNCR has a value of 0. 0x1 TXEMPTY Transmission Registers Empty 9 1 TXEMPTYSelect 0 As soon as data is written in TDR. 0x0 1 TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion ofsuch delay. 0x1 UNDES Underrun Error Status (Slave Mode Only) 10 1 TDR Transmit Data Register 0xC 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 LASTXFERSelect 0 No effect. 0x0 1 The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, thisallows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TDtransfer has completed. 0x1 PCS Peripheral Chip Select 16 4 TD Transmit Data 0 16 VERSION Version Register 0xFC 32 read-only n 0x0 0x0 MFN mfn 16 3 VERSION Version 0 12 WPCR Write Protection control Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key Password 8 24 WPKEYSelect VALUE SPI Write Protection Key Password 0x535049 WPSR Write Protection status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 3 WPVSSelect WRITE_WITH_WP The Write Protection has blocked a Write access to a protected register (since the last read). 0x1 SWRST_WITH_WP Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx). 0x2 UNEXPECTED_WRITE Write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select "i" was active) since the last read. 0x4 WPVSRC Write Protection Violation Source 8 8 TC0 Timer/Counter 0 TC 0x0 0x0 0x400 registers n TC00 55 TC01 56 TC02 57 BCR TC Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 SYNCSelect 0 No effect. 0x0 1 Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0x1 BMR TC Block Mode Register 0xC4 32 read-write n 0x0 0x0 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Select TCLK0 as clock signal 0. 0x0 NO_CLK Select no clock as clock signal 0. 0x1 TIOA1 Select TIOA1 as clock signal 0. 0x2 TIOA2 Select TIOA2 as clock signal 0. 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Select TCLK1 as clock signal 1. 0x0 NO_CLK Select no clock as clock signal 1. 0x1 TIOA0 Select TIOA0 as clock signal 1. 0x2 TIOA2 Select TIOA2 as clock signal 1. 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Select TCLK2 as clock signal 2. 0x0 NO_CLK Select no clock as clock signal 2. 0x1 TIOA0 Select TIOA0 as clock signal 2. 0x2 TIOA1 Select TIOA1 as clock signal 2. 0x3 CCR0 Channel Control Register Channel 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 CCR1 Channel Control Register Channel 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 CCR2 Channel Control Register Channel 0x80 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 CMR0 Channel Mode Register Channel 0x4 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 ACPA RA Compare Effect on TIOA 16 2 ACPASelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 ACPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 AEEVT External Event Effect on TIOA 20 2 AEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 ASWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 BCPBSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 BCPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BEEVT External Event Effect on TIOB 28 2 BEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 BSWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCDIS Counter Clock Disable with RC Compare 7 1 CPCDISSelect 0 Counter clock is not disabled when counter reaches RC. 0x0 1 Counter clock is disabled when counter reaches RC. 0x1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 CPCSTOPSelect 0 Counter clock is not stopped when counter reaches RC. 0x0 1 Counter clock is stopped when counter reaches RC. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 EEVT External Event Selection 10 2 EEVTSelect TIOB_INPUT TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. 0x0 XC0_OUTPUT XC0 output 0x1 XC1_OUTPUT XC1 output 0x2 XC2_OUTPUT XC2 output 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 ENETRG External Event Trigger Enable 12 1 ENETRGSelect 0 The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 0x0 1 The external event resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_DIV1_CLOCK TIMER_DIV1_CLOCK 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_DIV2_CLOCK TIMER_DIV2_CLOCK 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_DIV3_CLOCK TIMER_DIV3_CLOCK 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_DIV4_CLOCK TIMER_DIV4_CLOCK 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 TIMER_DIV5_CLOCK TIMER_DIV5_CLOCK 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE WAVE 15 1 WAVESelect 0 Waveform Mode is disabled (Capture Mode is enabled). 0x0 1 Waveform Mode is enabled. 0x1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP_NO_AUTO UP mode without automatic trigger on RC Compare 0x0 UPDOWN_NO_AUTO UPDOWN mode without automatic trigger on RC Compare 0x1 UP_AUTO UP mode with automatic trigger on RC Compare 0x2 UPDOWN_AUTO UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1 Channel Mode Register Channel 0x44 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 ACPA RA Compare Effect on TIOA 16 2 ACPASelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 ACPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 AEEVT External Event Effect on TIOA 20 2 AEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 ASWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 BCPBSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 BCPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BEEVT External Event Effect on TIOB 28 2 BEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 BSWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCDIS Counter Clock Disable with RC Compare 7 1 CPCDISSelect 0 Counter clock is not disabled when counter reaches RC. 0x0 1 Counter clock is disabled when counter reaches RC. 0x1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 CPCSTOPSelect 0 Counter clock is not stopped when counter reaches RC. 0x0 1 Counter clock is stopped when counter reaches RC. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 EEVT External Event Selection 10 2 EEVTSelect TIOB_INPUT TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. 0x0 XC0_OUTPUT XC0 output 0x1 XC1_OUTPUT XC1 output 0x2 XC2_OUTPUT XC2 output 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 ENETRG External Event Trigger Enable 12 1 ENETRGSelect 0 The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 0x0 1 The external event resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_DIV1_CLOCK TIMER_DIV1_CLOCK 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_DIV2_CLOCK TIMER_DIV2_CLOCK 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_DIV3_CLOCK TIMER_DIV3_CLOCK 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_DIV4_CLOCK TIMER_DIV4_CLOCK 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 TIMER_DIV5_CLOCK TIMER_DIV5_CLOCK 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE WAVE 15 1 WAVESelect 0 Waveform Mode is disabled (Capture Mode is enabled). 0x0 1 Waveform Mode is enabled. 0x1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP_NO_AUTO UP mode without automatic trigger on RC Compare 0x0 UPDOWN_NO_AUTO UPDOWN mode without automatic trigger on RC Compare 0x1 UP_AUTO UP mode with automatic trigger on RC Compare 0x2 UPDOWN_AUTO UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2 Channel Mode Register Channel 0x84 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 ACPA RA Compare Effect on TIOA 16 2 ACPASelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 ACPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 AEEVT External Event Effect on TIOA 20 2 AEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 ASWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 BCPBSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 BCPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BEEVT External Event Effect on TIOB 28 2 BEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 BSWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCDIS Counter Clock Disable with RC Compare 7 1 CPCDISSelect 0 Counter clock is not disabled when counter reaches RC. 0x0 1 Counter clock is disabled when counter reaches RC. 0x1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 CPCSTOPSelect 0 Counter clock is not stopped when counter reaches RC. 0x0 1 Counter clock is stopped when counter reaches RC. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 EEVT External Event Selection 10 2 EEVTSelect TIOB_INPUT TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. 0x0 XC0_OUTPUT XC0 output 0x1 XC1_OUTPUT XC1 output 0x2 XC2_OUTPUT XC2 output 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 ENETRG External Event Trigger Enable 12 1 ENETRGSelect 0 The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 0x0 1 The external event resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_DIV1_CLOCK TIMER_DIV1_CLOCK 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_DIV2_CLOCK TIMER_DIV2_CLOCK 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_DIV3_CLOCK TIMER_DIV3_CLOCK 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_DIV4_CLOCK TIMER_DIV4_CLOCK 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 TIMER_DIV5_CLOCK TIMER_DIV5_CLOCK 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE WAVE 15 1 WAVESelect 0 Waveform Mode is disabled (Capture Mode is enabled). 0x0 1 Waveform Mode is enabled. 0x1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP_NO_AUTO UP mode without automatic trigger on RC Compare 0x0 UPDOWN_NO_AUTO UPDOWN mode without automatic trigger on RC Compare 0x1 UP_AUTO UP mode with automatic trigger on RC Compare 0x2 UPDOWN_AUTO UPDOWN mode with automatic trigger on RC Compare 0x3 CV0 Counter Value Channel 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 16 CV1 Counter Value Channel 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 16 CV2 Counter Value Channel 0x90 32 read-only n 0x0 0x0 CV Counter Value 0 16 FEATURES Features Register 0xF8 32 read-only n 0x0 0x0 BRPBHSB Bridge Type is PB to HSB 9 1 CTRSIZE Counter Size 0 8 UPDNIMPL Up Down is Implemented 8 1 IDR0 Interrupt Disable Register Channel 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 IDR1 Interrupt Disable Register Channel 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 IDR2 Interrupt Disable Register Channel 0xA8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 IER0 Interrupt Enable Register Channel 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 IER1 Interrupt Enable Register Channel 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 IER2 Interrupt Enable Register Channel 0xA4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 IMR0 Interrupt Mask Register Channel 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 IMR1 Interrupt Mask Register Channel 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 IMR2 Interrupt Mask Register Channel 0xAC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 RA0 Register A Channel 0x14 32 read-write n 0x0 0x0 RA Register A 0 16 RA1 Register A Channel 0x54 32 read-write n 0x0 0x0 RA Register A 0 16 RA2 Register A Channel 0x94 32 read-write n 0x0 0x0 RA Register A 0 16 RB0 Register B Channel 0x18 32 read-write n 0x0 0x0 RB Register B 0 16 RB1 Register B Channel 0x58 32 read-write n 0x0 0x0 RB Register B 0 16 RB2 Register B Channel 0x98 32 read-write n 0x0 0x0 RB Register B 0 16 RC0 Register C Channel 0x1C 32 read-write n 0x0 0x0 RC Register C 0 16 RC1 Register C Channel 0x5C 32 read-write n 0x0 0x0 RC Register C 0 16 RC2 Register C Channel 0x9C 32 read-write n 0x0 0x0 RC Register C 0 16 SMMR0 Stepper Motor Mode Register 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 SMMR1 Stepper Motor Mode Register 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 SMMR2 Stepper Motor Mode Register 0x88 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 SR0 Status Register Channel 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 SR1 Status Register Channel 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 SR2 Status Register Channel 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 TC_BCR TC Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 SYNCSelect 0 No effect. 0x0 1 Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0x1 TC_BMR TC Block Mode Register 0xC4 32 read-write n 0x0 0x0 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Select TCLK0 as clock signal 0. 0x0 NO_CLK Select no clock as clock signal 0. 0x1 TIOA1 Select TIOA1 as clock signal 0. 0x2 TIOA2 Select TIOA2 as clock signal 0. 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Select TCLK1 as clock signal 1. 0x0 NO_CLK Select no clock as clock signal 1. 0x1 TIOA0 Select TIOA0 as clock signal 1. 0x2 TIOA2 Select TIOA2 as clock signal 1. 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Select TCLK2 as clock signal 2. 0x0 NO_CLK Select no clock as clock signal 2. 0x1 TIOA0 Select TIOA0 as clock signal 2. 0x2 TIOA1 Select TIOA1 as clock signal 2. 0x3 TC_CCR0 Channel Control Register Channel 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 TC_CCR1 Channel Control Register Channel 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 TC_CCR2 Channel Control Register Channel 0xC0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 TC_CMR0 Channel Mode Register Channel CAPTURE 0x8 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE Wave 15 1 WAVESelect 0 Capture Mode is enabled. 0x0 1 Capture Mode is disabled (Waveform Mode is enabled). 0x1 TC_CMR1 Channel Mode Register Channel CAPTURE 0x4C 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE Wave 15 1 WAVESelect 0 Capture Mode is enabled. 0x0 1 Capture Mode is disabled (Waveform Mode is enabled). 0x1 TC_CMR2 Channel Mode Register Channel CAPTURE 0xD0 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE Wave 15 1 WAVESelect 0 Capture Mode is enabled. 0x0 1 Capture Mode is disabled (Waveform Mode is enabled). 0x1 TC_CV0 Counter Value Channel 0x20 32 read-only n 0x0 0x0 CV Counter Value 0 16 TC_CV1 Counter Value Channel 0x70 32 read-only n 0x0 0x0 CV Counter Value 0 16 TC_CV2 Counter Value Channel 0x100 32 read-only n 0x0 0x0 CV Counter Value 0 16 TC_FEATURES Features Register 0xF8 32 read-only n 0x0 0x0 BRPBHSB Bridge Type is PB to HSB 9 1 CTRSIZE Counter Size 0 8 UPDNIMPL Up Down is Implemented 8 1 TC_IDR0 Interrupt Disable Register Channel 0x50 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 TC_IDR1 Interrupt Disable Register Channel 0xB8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 TC_IDR2 Interrupt Disable Register Channel 0x160 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 TC_IER0 Interrupt Enable Register Channel 0x48 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 TC_IER1 Interrupt Enable Register Channel 0xAC 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 TC_IER2 Interrupt Enable Register Channel 0x150 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 TC_IMR0 Interrupt Mask Register Channel 0x58 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 TC_IMR1 Interrupt Mask Register Channel 0xC4 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 TC_IMR2 Interrupt Mask Register Channel 0x170 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 TC_RA0 Register A Channel 0x28 32 read-write n 0x0 0x0 RA Register A 0 16 TC_RA1 Register A Channel 0x7C 32 read-write n 0x0 0x0 RA Register A 0 16 TC_RA2 Register A Channel 0x110 32 read-write n 0x0 0x0 RA Register A 0 16 TC_RB0 Register B Channel 0x30 32 read-write n 0x0 0x0 RB Register B 0 16 TC_RB1 Register B Channel 0x88 32 read-write n 0x0 0x0 RB Register B 0 16 TC_RB2 Register B Channel 0x120 32 read-write n 0x0 0x0 RB Register B 0 16 TC_RC0 Register C Channel 0x38 32 read-write n 0x0 0x0 RC Register C 0 16 TC_RC1 Register C Channel 0x94 32 read-write n 0x0 0x0 RC Register C 0 16 TC_RC2 Register C Channel 0x130 32 read-write n 0x0 0x0 RC Register C 0 16 TC_SMMR0 Stepper Motor Mode Register 0x10 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_SMMR1 Stepper Motor Mode Register 0x58 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_SMMR2 Stepper Motor Mode Register 0xE0 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_SR0 Status Register Channel 0x40 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 TC_SR1 Status Register Channel 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 TC_SR2 Status Register Channel 0x140 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 TC_VERSION Version Register 0xFC 32 read-only n 0x0 0x0 VARIANT Reserved. Value subject to change. No functionality associated. 16 4 VERSION Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. 0 12 TC_WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPKEY Write Protect Key 8 24 VERSION Version Register 0xFC 32 read-only n 0x0 0x0 VARIANT Reserved. Value subject to change. No functionality associated. 16 4 VERSION Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. 0 12 WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPKEY Write Protect Key 8 24 TC1 Timer/Counter 1 TC 0x0 0x0 0x400 registers n TC10 58 TC11 59 TC12 60 BCR TC Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 SYNCSelect 0 No effect. 0x0 1 Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0x1 BMR TC Block Mode Register 0xC4 32 read-write n 0x0 0x0 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Select TCLK0 as clock signal 0. 0x0 NO_CLK Select no clock as clock signal 0. 0x1 TIOA1 Select TIOA1 as clock signal 0. 0x2 TIOA2 Select TIOA2 as clock signal 0. 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Select TCLK1 as clock signal 1. 0x0 NO_CLK Select no clock as clock signal 1. 0x1 TIOA0 Select TIOA0 as clock signal 1. 0x2 TIOA2 Select TIOA2 as clock signal 1. 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Select TCLK2 as clock signal 2. 0x0 NO_CLK Select no clock as clock signal 2. 0x1 TIOA0 Select TIOA0 as clock signal 2. 0x2 TIOA1 Select TIOA1 as clock signal 2. 0x3 CCR0 Channel Control Register Channel 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 CCR1 Channel Control Register Channel 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 CCR2 Channel Control Register Channel 0x80 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 CMR0 Channel Mode Register Channel 0x4 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 ACPA RA Compare Effect on TIOA 16 2 ACPASelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 ACPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 AEEVT External Event Effect on TIOA 20 2 AEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 ASWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 BCPBSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 BCPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BEEVT External Event Effect on TIOB 28 2 BEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 BSWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCDIS Counter Clock Disable with RC Compare 7 1 CPCDISSelect 0 Counter clock is not disabled when counter reaches RC. 0x0 1 Counter clock is disabled when counter reaches RC. 0x1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 CPCSTOPSelect 0 Counter clock is not stopped when counter reaches RC. 0x0 1 Counter clock is stopped when counter reaches RC. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 EEVT External Event Selection 10 2 EEVTSelect TIOB_INPUT TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. 0x0 XC0_OUTPUT XC0 output 0x1 XC1_OUTPUT XC1 output 0x2 XC2_OUTPUT XC2 output 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 ENETRG External Event Trigger Enable 12 1 ENETRGSelect 0 The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 0x0 1 The external event resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_DIV1_CLOCK TIMER_DIV1_CLOCK 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_DIV2_CLOCK TIMER_DIV2_CLOCK 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_DIV3_CLOCK TIMER_DIV3_CLOCK 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_DIV4_CLOCK TIMER_DIV4_CLOCK 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 TIMER_DIV5_CLOCK TIMER_DIV5_CLOCK 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE WAVE 15 1 WAVESelect 0 Waveform Mode is disabled (Capture Mode is enabled). 0x0 1 Waveform Mode is enabled. 0x1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP_NO_AUTO UP mode without automatic trigger on RC Compare 0x0 UPDOWN_NO_AUTO UPDOWN mode without automatic trigger on RC Compare 0x1 UP_AUTO UP mode with automatic trigger on RC Compare 0x2 UPDOWN_AUTO UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1 Channel Mode Register Channel 0x44 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 ACPA RA Compare Effect on TIOA 16 2 ACPASelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 ACPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 AEEVT External Event Effect on TIOA 20 2 AEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 ASWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 BCPBSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 BCPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BEEVT External Event Effect on TIOB 28 2 BEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 BSWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCDIS Counter Clock Disable with RC Compare 7 1 CPCDISSelect 0 Counter clock is not disabled when counter reaches RC. 0x0 1 Counter clock is disabled when counter reaches RC. 0x1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 CPCSTOPSelect 0 Counter clock is not stopped when counter reaches RC. 0x0 1 Counter clock is stopped when counter reaches RC. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 EEVT External Event Selection 10 2 EEVTSelect TIOB_INPUT TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. 0x0 XC0_OUTPUT XC0 output 0x1 XC1_OUTPUT XC1 output 0x2 XC2_OUTPUT XC2 output 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 ENETRG External Event Trigger Enable 12 1 ENETRGSelect 0 The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 0x0 1 The external event resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_DIV1_CLOCK TIMER_DIV1_CLOCK 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_DIV2_CLOCK TIMER_DIV2_CLOCK 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_DIV3_CLOCK TIMER_DIV3_CLOCK 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_DIV4_CLOCK TIMER_DIV4_CLOCK 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 TIMER_DIV5_CLOCK TIMER_DIV5_CLOCK 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE WAVE 15 1 WAVESelect 0 Waveform Mode is disabled (Capture Mode is enabled). 0x0 1 Waveform Mode is enabled. 0x1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP_NO_AUTO UP mode without automatic trigger on RC Compare 0x0 UPDOWN_NO_AUTO UPDOWN mode without automatic trigger on RC Compare 0x1 UP_AUTO UP mode with automatic trigger on RC Compare 0x2 UPDOWN_AUTO UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2 Channel Mode Register Channel 0x84 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 ACPA RA Compare Effect on TIOA 16 2 ACPASelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 ACPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 AEEVT External Event Effect on TIOA 20 2 AEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 ASWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 BCPBSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 BCPCSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BEEVT External Event Effect on TIOB 28 2 BEEVTSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 BSWTRGSelect NONE none 0x0 SET set 0x1 CLEAR clear 0x2 TOGGLE toggle 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCDIS Counter Clock Disable with RC Compare 7 1 CPCDISSelect 0 Counter clock is not disabled when counter reaches RC. 0x0 1 Counter clock is disabled when counter reaches RC. 0x1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 CPCSTOPSelect 0 Counter clock is not stopped when counter reaches RC. 0x0 1 Counter clock is stopped when counter reaches RC. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 EEVT External Event Selection 10 2 EEVTSelect TIOB_INPUT TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. 0x0 XC0_OUTPUT XC0 output 0x1 XC1_OUTPUT XC1 output 0x2 XC2_OUTPUT XC2 output 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 ENETRG External Event Trigger Enable 12 1 ENETRGSelect 0 The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 0x0 1 The external event resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_DIV1_CLOCK TIMER_DIV1_CLOCK 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_DIV2_CLOCK TIMER_DIV2_CLOCK 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_DIV3_CLOCK TIMER_DIV3_CLOCK 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_DIV4_CLOCK TIMER_DIV4_CLOCK 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 TIMER_DIV5_CLOCK TIMER_DIV5_CLOCK 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE WAVE 15 1 WAVESelect 0 Waveform Mode is disabled (Capture Mode is enabled). 0x0 1 Waveform Mode is enabled. 0x1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP_NO_AUTO UP mode without automatic trigger on RC Compare 0x0 UPDOWN_NO_AUTO UPDOWN mode without automatic trigger on RC Compare 0x1 UP_AUTO UP mode with automatic trigger on RC Compare 0x2 UPDOWN_AUTO UPDOWN mode with automatic trigger on RC Compare 0x3 CV0 Counter Value Channel 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 16 CV1 Counter Value Channel 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 16 CV2 Counter Value Channel 0x90 32 read-only n 0x0 0x0 CV Counter Value 0 16 FEATURES Features Register 0xF8 32 read-only n 0x0 0x0 BRPBHSB Bridge Type is PB to HSB 9 1 CTRSIZE Counter Size 0 8 UPDNIMPL Up Down is Implemented 8 1 IDR0 Interrupt Disable Register Channel 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 IDR1 Interrupt Disable Register Channel 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 IDR2 Interrupt Disable Register Channel 0xA8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 IER0 Interrupt Enable Register Channel 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 IER1 Interrupt Enable Register Channel 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 IER2 Interrupt Enable Register Channel 0xA4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 IMR0 Interrupt Mask Register Channel 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 IMR1 Interrupt Mask Register Channel 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 IMR2 Interrupt Mask Register Channel 0xAC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 RA0 Register A Channel 0x14 32 read-write n 0x0 0x0 RA Register A 0 16 RA1 Register A Channel 0x54 32 read-write n 0x0 0x0 RA Register A 0 16 RA2 Register A Channel 0x94 32 read-write n 0x0 0x0 RA Register A 0 16 RB0 Register B Channel 0x18 32 read-write n 0x0 0x0 RB Register B 0 16 RB1 Register B Channel 0x58 32 read-write n 0x0 0x0 RB Register B 0 16 RB2 Register B Channel 0x98 32 read-write n 0x0 0x0 RB Register B 0 16 RC0 Register C Channel 0x1C 32 read-write n 0x0 0x0 RC Register C 0 16 RC1 Register C Channel 0x5C 32 read-write n 0x0 0x0 RC Register C 0 16 RC2 Register C Channel 0x9C 32 read-write n 0x0 0x0 RC Register C 0 16 SMMR0 Stepper Motor Mode Register 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 SMMR1 Stepper Motor Mode Register 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 SMMR2 Stepper Motor Mode Register 0x88 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 SR0 Status Register Channel 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 SR1 Status Register Channel 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 SR2 Status Register Channel 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 TC_BCR TC Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 SYNCSelect 0 No effect. 0x0 1 Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0x1 TC_BMR TC Block Mode Register 0xC4 32 read-write n 0x0 0x0 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Select TCLK0 as clock signal 0. 0x0 NO_CLK Select no clock as clock signal 0. 0x1 TIOA1 Select TIOA1 as clock signal 0. 0x2 TIOA2 Select TIOA2 as clock signal 0. 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Select TCLK1 as clock signal 1. 0x0 NO_CLK Select no clock as clock signal 1. 0x1 TIOA0 Select TIOA0 as clock signal 1. 0x2 TIOA2 Select TIOA2 as clock signal 1. 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Select TCLK2 as clock signal 2. 0x0 NO_CLK Select no clock as clock signal 2. 0x1 TIOA0 Select TIOA0 as clock signal 2. 0x2 TIOA1 Select TIOA1 as clock signal 2. 0x3 TC_CCR0 Channel Control Register Channel 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 TC_CCR1 Channel Control Register Channel 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 TC_CCR2 Channel Control Register Channel 0xC0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKDISSelect 0 No effect. 0x0 1 Disables the clock. 0x1 CLKEN Counter Clock Enable Command 0 1 CLKENSelect 0 No effect. 0x0 1 Enables the clock if CLKDIS is not 1. 0x1 SWTRG Software Trigger Command 2 1 SWTRGSelect 0 No effect. 0x0 1 A software trigger is performed:the counter is reset and clock is started. 0x1 TC_CMR0 Channel Mode Register Channel CAPTURE 0x8 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE Wave 15 1 WAVESelect 0 Capture Mode is enabled. 0x0 1 Capture Mode is disabled (Waveform Mode is enabled). 0x1 TC_CMR1 Channel Mode Register Channel CAPTURE 0x4C 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE Wave 15 1 WAVESelect 0 Capture Mode is enabled. 0x0 1 Capture Mode is disabled (Waveform Mode is enabled). 0x1 TC_CMR2 Channel Mode Register Channel CAPTURE 0xD0 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 ABETRGSelect 0 TIOB is used as an external trigger. 0x0 1 TIOA is used as an external trigger. 0x1 BURST Burst Signal Selection 4 2 BURSTSelect NOT_GATED The clock is not gated by an external signal. 0x0 CLK_AND_XC0 XC0 is ANDed with the selected clock. 0x1 CLK_AND_XC1 XC1 is ANDed with the selected clock. 0x2 CLK_AND_XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CLKISelect 0 Counter is incremented on rising edge of the clock. 0x0 1 Counter is incremented on falling edge of the clock. 0x1 CPCTRG RC Compare Trigger Enable 14 1 CPCTRGSelect 0 RC Compare has no effect on the counter and its clock. 0x0 1 RC Compare resets the counter and starts the counter clock. 0x1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NO_EDGE none 0x0 POS_EDGE rising edge 0x1 NEG_EDGE falling edge 0x2 BOTH_EDGES each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBDISSelect 0 Counter clock is not disabled when RB loading occurs. 0x0 1 Counter clock is disabled when RB loading occurs. 0x1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDBSTOPSelect 0 Counter clock is not stopped when RB loading occurs. 0x0 1 Counter clock is stopped when RB loading occurs. 0x1 LDRA RA Loading Selection 16 2 LDRASelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 LDRB RB Loading Selection 18 2 LDRBSelect NO_EDGE none 0x0 POS_EDGE_TIOA rising edge of TIOA 0x1 NEG_EDGE_TIOA falling edge of TIOA 0x2 BOTH_EDGES_TIOA each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 TIMER_CLOCK1 0x0 TIMER_CLOCK2 TIMER_CLOCK2 0x1 TIMER_CLOCK3 TIMER_CLOCK3 0x2 TIMER_CLOCK4 TIMER_CLOCK4 0x3 TIMER_CLOCK5 TIMER_CLOCK5 0x4 XC0 XC0 0x5 XC1 XC1 0x6 XC2 XC2 0x7 WAVE Wave 15 1 WAVESelect 0 Capture Mode is enabled. 0x0 1 Capture Mode is disabled (Waveform Mode is enabled). 0x1 TC_CV0 Counter Value Channel 0x20 32 read-only n 0x0 0x0 CV Counter Value 0 16 TC_CV1 Counter Value Channel 0x70 32 read-only n 0x0 0x0 CV Counter Value 0 16 TC_CV2 Counter Value Channel 0x100 32 read-only n 0x0 0x0 CV Counter Value 0 16 TC_FEATURES Features Register 0xF8 32 read-only n 0x0 0x0 BRPBHSB Bridge Type is PB to HSB 9 1 CTRSIZE Counter Size 0 8 UPDNIMPL Up Down is Implemented 8 1 TC_IDR0 Interrupt Disable Register Channel 0x50 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 TC_IDR1 Interrupt Disable Register Channel 0xB8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 TC_IDR2 Interrupt Disable Register Channel 0x160 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Disables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Disables the RA Compare Interrupt (if WAVE:1). 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Disables the RB Compare Interrupt (if WAVE:1). 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Disables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Disables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Disables the RA Load Interrupt (if WAVE:0). 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Disables the RB Load Interrupt (if WAVE:0). 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Disables the Load Overrun Interrupt (if WAVE:0). 0x1 TC_IER0 Interrupt Enable Register Channel 0x48 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 TC_IER1 Interrupt Enable Register Channel 0xAC 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 TC_IER2 Interrupt Enable Register Channel 0x150 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 No effect. 0x0 1 Enables the Counter Overflow Interrupt. 0x1 CPAS RA Compare 2 1 CPASSelect 0 No effect. 0x0 1 Enables the RA Compare Interrupt. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 No effect. 0x0 1 Enables the RB Compare Interrupt. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 No effect. 0x0 1 Enables the RC Compare Interrupt. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 No effect. 0x0 1 Enables the External Trigger Interrupt. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 No effect. 0x0 1 Enables the RA Load Interrupt. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 No effect. 0x0 1 Enables the RB Load Interrupt. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 No effect. 0x0 1 Enables the Load Overrun Interrupt. 0x1 TC_IMR0 Interrupt Mask Register Channel 0x58 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 TC_IMR1 Interrupt Mask Register Channel 0xC4 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 TC_IMR2 Interrupt Mask Register Channel 0x170 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 COVFSSelect 0 The Counter Overflow Interrupt is disabled. 0x0 1 The Counter Overflow Interrupt is enabled. 0x1 CPAS RA Compare 2 1 CPASSelect 0 The RA Compare Interrupt is disabled. 0x0 1 The RA Compare Interrupt is enabled. 0x1 CPBS RB Compare 3 1 CPBSSelect 0 The RB Compare Interrupt is disabled. 0x0 1 The RB Compare Interrupt is enabled. 0x1 CPCS RC Compare 4 1 CPCSSelect 0 The RC Compare Interrupt is disabled. 0x0 1 The RC Compare Interrupt is enabled. 0x1 ETRGS External Trigger 7 1 ETRGSSelect 0 The External Trigger Interrupt is disabled. 0x0 1 The External Trigger Interrupt is enabled. 0x1 LDRAS RA Loading 5 1 LDRASSelect 0 The Load RA Interrupt is disabled. 0x0 1 The Load RA Interrupt is enabled. 0x1 LDRBS RB Loading 6 1 LDRBSSelect 0 The Load RB Interrupt is disabled. 0x0 1 The Load RB Interrupt is enabled. 0x1 LOVRS Load Overrun 1 1 LOVRSSelect 0 The Load Overrun Interrupt is disabled. 0x0 1 The Load Overrun Interrupt is enabled. 0x1 TC_RA0 Register A Channel 0x28 32 read-write n 0x0 0x0 RA Register A 0 16 TC_RA1 Register A Channel 0x7C 32 read-write n 0x0 0x0 RA Register A 0 16 TC_RA2 Register A Channel 0x110 32 read-write n 0x0 0x0 RA Register A 0 16 TC_RB0 Register B Channel 0x30 32 read-write n 0x0 0x0 RB Register B 0 16 TC_RB1 Register B Channel 0x88 32 read-write n 0x0 0x0 RB Register B 0 16 TC_RB2 Register B Channel 0x120 32 read-write n 0x0 0x0 RB Register B 0 16 TC_RC0 Register C Channel 0x38 32 read-write n 0x0 0x0 RC Register C 0 16 TC_RC1 Register C Channel 0x94 32 read-write n 0x0 0x0 RC Register C 0 16 TC_RC2 Register C Channel 0x130 32 read-write n 0x0 0x0 RC Register C 0 16 TC_SMMR0 Stepper Motor Mode Register 0x10 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_SMMR1 Stepper Motor Mode Register 0x58 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_SMMR2 Stepper Motor Mode Register 0xE0 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_SR0 Status Register Channel 0x40 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 TC_SR1 Status Register Channel 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 TC_SR2 Status Register Channel 0x140 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 CLKSTASelect 0 Clock is disabled. 0x0 1 Clock is enabled. 0x1 COVFS Counter Overflow Status 0 1 COVFSSelect 0 No counter overflow has occurred since the last read of the Status Register. 0x0 1 A counter overflow has occurred since the last read of the Status Register. 0x1 CPAS RA Compare Status 2 1 CPASSelect 0 RA Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RA Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPBS RB Compare Status 3 1 CPBSSelect 0 RB Compare has not occurred since the last read of the Status Register or WAVE:0. 0x0 1 RB Compare has occurred since the last read of the Status Register, if WAVE:1. 0x1 CPCS RC Compare Status 4 1 CPCSSelect 0 RC Compare has not occurred since the last read of the Status Register. 0x0 1 RC Compare has occurred since the last read of the Status Register. 0x1 ETRGS External Trigger Status 7 1 ETRGSSelect 0 External trigger has not occurred since the last read of the Status Register. 0x0 1 External trigger has occurred since the last read of the Status Register. 0x1 LDRAS RA Loading Status 5 1 LDRASSelect 0 RA Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LDRBS RB Loading Status 6 1 LDRBSSelect 0 RB Load has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RB Load has occurred since the last read of the Status Register, if WAVE:0. 0x1 LOVRS Load Overrun Status 1 1 LOVRSSelect 0 Load overrun has not occurred since the last read of the Status Register or WAVE:1. 0x0 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. 0x1 MTIOA TIOA Mirror 17 1 MTIOASelect 0 TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. 0x0 1 TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. 0x1 MTIOB TIOB Mirror 18 1 MTIOBSelect 0 TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. 0x0 1 TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. 0x1 TC_VERSION Version Register 0xFC 32 read-only n 0x0 0x0 VARIANT Reserved. Value subject to change. No functionality associated. 16 4 VERSION Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. 0 12 TC_WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPKEY Write Protect Key 8 24 VERSION Version Register 0xFC 32 read-only n 0x0 0x0 VARIANT Reserved. Value subject to change. No functionality associated. 16 4 VERSION Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. 0 12 WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPKEY Write Protect Key 8 24 TRNG True Random Number Generator TRNG 0x0 0x0 0x400 registers n TRNG 73 CR Control Register 0x0 32 write-only n 0x0 0x0 ENABLE Enables the TRNG to provide random values 0 1 write-only KEY Security Key 8 24 IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 write-only IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 write-only IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Status 0 1 read-only ODATA Output Data Register 0x50 32 read-only n 0x0 0x0 ODATA Output Data 0 1 read-only VERSION Version Register 0xFC 32 read-only n 0x0 0x0 VARIANT Variant Number 16 3 read-only VERSION Version Number 0 12 read-only TWIM0 Two-wire Master Interface 0 TWIM 0x0 0x0 0x400 registers n TWIM0 61 CMDR Command Register 0xC 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 CR Control Register 0x0 32 write-only n 0x0 0x0 MDIS Master Disable 1 1 MEN Master Enable 0 1 SMDIS SMBus Disable 5 1 SMEN SMBus Enable 4 1 STOP Stop the current transfer 8 1 SWRST Software Reset 7 1 CWGR Clock Waveform Generator Register 0x4 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 HSCWGR HS-mode Clock Waveform Generator 0x38 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 HSSRR HS-mode Slew Rate Register 0x40 32 read-write n 0x0 0x0 CLDRIVEH Clock Drive Strength HIGH 20 2 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 NCMDR Next Command Register 0x10 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 PR Parameter Register 0x30 32 read-only n 0x0 0x0 HS HS-mode 0 1 RHR Receive Holding Register 0x14 32 read-only n 0x0 0x0 RXDATA Received Data 0 8 SCR Status Clear Register 0x2C 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 CCOMP Command Complete 3 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 PECERR PEC Error 13 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 SMBTR SMBus Timing Register 0x8 32 read-write n 0x0 0x0 EXP SMBus Timeout Clock prescaler 28 4 THMAX Clock High maximum cycles 16 8 TLOWM Master Clock stretch maximum cycles 8 8 TLOWS Slave Clock stretch maximum cycles 0 8 SR Status Register 0x1C 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 MENB Master Interface Enable 16 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 SRR Slew Rate Register 0x3C 32 read-write n 0x0 0x0 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 THR Transmit Holding Register 0x18 32 write-only n 0x0 0x0 TXDATA Data to Transmit 0 8 TWIM_CMDR Command Register 0xC 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 TWIM_CR Control Register 0x0 32 write-only n 0x0 0x0 MDIS Master Disable 1 1 MEN Master Enable 0 1 SMDIS SMBus Disable 5 1 SMEN SMBus Enable 4 1 STOP Stop the current transfer 8 1 SWRST Software Reset 7 1 TWIM_CWGR Clock Waveform Generator Register 0x4 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 TWIM_HSCWGR HS-mode Clock Waveform Generator 0x38 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 TWIM_HSSRR HS-mode Slew Rate Register 0x40 32 read-write n 0x0 0x0 CLDRIVEH Clock Drive Strength HIGH 20 2 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIM_IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_NCMDR Next Command Register 0x10 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 TWIM_PR Parameter Register 0x30 32 read-only n 0x0 0x0 HS HS-mode 0 1 TWIM_RHR Receive Holding Register 0x14 32 read-only n 0x0 0x0 RXDATA Received Data 0 8 TWIM_SCR Status Clear Register 0x2C 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 CCOMP Command Complete 3 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 PECERR PEC Error 13 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TWIM_SMBTR SMBus Timing Register 0x8 32 read-write n 0x0 0x0 EXP SMBus Timeout Clock prescaler 28 4 THMAX Clock High maximum cycles 16 8 TLOWM Master Clock stretch maximum cycles 8 8 TLOWS Slave Clock stretch maximum cycles 0 8 TWIM_SR Status Register 0x1C 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 MENB Master Interface Enable 16 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_SRR Slew Rate Register 0x3C 32 read-write n 0x0 0x0 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIM_THR Transmit Holding Register 0x18 32 write-only n 0x0 0x0 TXDATA Data to Transmit 0 8 TWIM_VR Version Register 0x34 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 VR Version Register 0x34 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 TWIM1 Two-wire Master Interface 1 TWIM 0x0 0x0 0x400 registers n TWIM1 63 CMDR Command Register 0xC 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 CR Control Register 0x0 32 write-only n 0x0 0x0 MDIS Master Disable 1 1 MEN Master Enable 0 1 SMDIS SMBus Disable 5 1 SMEN SMBus Enable 4 1 STOP Stop the current transfer 8 1 SWRST Software Reset 7 1 CWGR Clock Waveform Generator Register 0x4 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 HSCWGR HS-mode Clock Waveform Generator 0x38 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 HSSRR HS-mode Slew Rate Register 0x40 32 read-write n 0x0 0x0 CLDRIVEH Clock Drive Strength HIGH 20 2 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 NCMDR Next Command Register 0x10 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 PR Parameter Register 0x30 32 read-only n 0x0 0x0 HS HS-mode 0 1 RHR Receive Holding Register 0x14 32 read-only n 0x0 0x0 RXDATA Received Data 0 8 SCR Status Clear Register 0x2C 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 CCOMP Command Complete 3 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 PECERR PEC Error 13 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 SMBTR SMBus Timing Register 0x8 32 read-write n 0x0 0x0 EXP SMBus Timeout Clock prescaler 28 4 THMAX Clock High maximum cycles 16 8 TLOWM Master Clock stretch maximum cycles 8 8 TLOWS Slave Clock stretch maximum cycles 0 8 SR Status Register 0x1C 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 MENB Master Interface Enable 16 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 SRR Slew Rate Register 0x3C 32 read-write n 0x0 0x0 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 THR Transmit Holding Register 0x18 32 write-only n 0x0 0x0 TXDATA Data to Transmit 0 8 TWIM_CMDR Command Register 0xC 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 TWIM_CR Control Register 0x0 32 write-only n 0x0 0x0 MDIS Master Disable 1 1 MEN Master Enable 0 1 SMDIS SMBus Disable 5 1 SMEN SMBus Enable 4 1 STOP Stop the current transfer 8 1 SWRST Software Reset 7 1 TWIM_CWGR Clock Waveform Generator Register 0x4 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 TWIM_HSCWGR HS-mode Clock Waveform Generator 0x38 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 TWIM_HSSRR HS-mode Slew Rate Register 0x40 32 read-write n 0x0 0x0 CLDRIVEH Clock Drive Strength HIGH 20 2 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIM_IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_NCMDR Next Command Register 0x10 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 TWIM_PR Parameter Register 0x30 32 read-only n 0x0 0x0 HS HS-mode 0 1 TWIM_RHR Receive Holding Register 0x14 32 read-only n 0x0 0x0 RXDATA Received Data 0 8 TWIM_SCR Status Clear Register 0x2C 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 CCOMP Command Complete 3 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 PECERR PEC Error 13 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TWIM_SMBTR SMBus Timing Register 0x8 32 read-write n 0x0 0x0 EXP SMBus Timeout Clock prescaler 28 4 THMAX Clock High maximum cycles 16 8 TLOWM Master Clock stretch maximum cycles 8 8 TLOWS Slave Clock stretch maximum cycles 0 8 TWIM_SR Status Register 0x1C 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 MENB Master Interface Enable 16 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_SRR Slew Rate Register 0x3C 32 read-write n 0x0 0x0 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIM_THR Transmit Holding Register 0x18 32 write-only n 0x0 0x0 TXDATA Data to Transmit 0 8 TWIM_VR Version Register 0x34 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 VR Version Register 0x34 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 TWIM2 Two-wire Master Interface 2 TWIM 0x0 0x0 0x400 registers n TWIM2 77 CMDR Command Register 0xC 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 CR Control Register 0x0 32 write-only n 0x0 0x0 MDIS Master Disable 1 1 MEN Master Enable 0 1 SMDIS SMBus Disable 5 1 SMEN SMBus Enable 4 1 STOP Stop the current transfer 8 1 SWRST Software Reset 7 1 CWGR Clock Waveform Generator Register 0x4 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 HSCWGR HS-mode Clock Waveform Generator 0x38 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 HSSRR HS-mode Slew Rate Register 0x40 32 read-write n 0x0 0x0 CLDRIVEH Clock Drive Strength HIGH 20 2 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 NCMDR Next Command Register 0x10 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 PR Parameter Register 0x30 32 read-only n 0x0 0x0 HS HS-mode 0 1 RHR Receive Holding Register 0x14 32 read-only n 0x0 0x0 RXDATA Received Data 0 8 SCR Status Clear Register 0x2C 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 CCOMP Command Complete 3 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 PECERR PEC Error 13 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 SMBTR SMBus Timing Register 0x8 32 read-write n 0x0 0x0 EXP SMBus Timeout Clock prescaler 28 4 THMAX Clock High maximum cycles 16 8 TLOWM Master Clock stretch maximum cycles 8 8 TLOWS Slave Clock stretch maximum cycles 0 8 SR Status Register 0x1C 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 MENB Master Interface Enable 16 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 SRR Slew Rate Register 0x3C 32 read-write n 0x0 0x0 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 THR Transmit Holding Register 0x18 32 write-only n 0x0 0x0 TXDATA Data to Transmit 0 8 TWIM_CMDR Command Register 0xC 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 TWIM_CR Control Register 0x0 32 write-only n 0x0 0x0 MDIS Master Disable 1 1 MEN Master Enable 0 1 SMDIS SMBus Disable 5 1 SMEN SMBus Enable 4 1 STOP Stop the current transfer 8 1 SWRST Software Reset 7 1 TWIM_CWGR Clock Waveform Generator Register 0x4 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 TWIM_HSCWGR HS-mode Clock Waveform Generator 0x38 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 TWIM_HSSRR HS-mode Slew Rate Register 0x40 32 read-write n 0x0 0x0 CLDRIVEH Clock Drive Strength HIGH 20 2 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIM_IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_NCMDR Next Command Register 0x10 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 TWIM_PR Parameter Register 0x30 32 read-only n 0x0 0x0 HS HS-mode 0 1 TWIM_RHR Receive Holding Register 0x14 32 read-only n 0x0 0x0 RXDATA Received Data 0 8 TWIM_SCR Status Clear Register 0x2C 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 CCOMP Command Complete 3 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 PECERR PEC Error 13 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TWIM_SMBTR SMBus Timing Register 0x8 32 read-write n 0x0 0x0 EXP SMBus Timeout Clock prescaler 28 4 THMAX Clock High maximum cycles 16 8 TLOWM Master Clock stretch maximum cycles 8 8 TLOWS Slave Clock stretch maximum cycles 0 8 TWIM_SR Status Register 0x1C 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 MENB Master Interface Enable 16 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_SRR Slew Rate Register 0x3C 32 read-write n 0x0 0x0 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIM_THR Transmit Holding Register 0x18 32 write-only n 0x0 0x0 TXDATA Data to Transmit 0 8 TWIM_VR Version Register 0x34 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 VR Version Register 0x34 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 TWIM3 Two-wire Master Interface 3 TWIM 0x0 0x0 0x400 registers n TWIM3 78 CMDR Command Register 0xC 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 CR Control Register 0x0 32 write-only n 0x0 0x0 MDIS Master Disable 1 1 MEN Master Enable 0 1 SMDIS SMBus Disable 5 1 SMEN SMBus Enable 4 1 STOP Stop the current transfer 8 1 SWRST Software Reset 7 1 CWGR Clock Waveform Generator Register 0x4 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 HSCWGR HS-mode Clock Waveform Generator 0x38 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 HSSRR HS-mode Slew Rate Register 0x40 32 read-write n 0x0 0x0 CLDRIVEH Clock Drive Strength HIGH 20 2 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 NCMDR Next Command Register 0x10 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 PR Parameter Register 0x30 32 read-only n 0x0 0x0 HS HS-mode 0 1 RHR Receive Holding Register 0x14 32 read-only n 0x0 0x0 RXDATA Received Data 0 8 SCR Status Clear Register 0x2C 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 CCOMP Command Complete 3 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 PECERR PEC Error 13 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 SMBTR SMBus Timing Register 0x8 32 read-write n 0x0 0x0 EXP SMBus Timeout Clock prescaler 28 4 THMAX Clock High maximum cycles 16 8 TLOWM Master Clock stretch maximum cycles 8 8 TLOWS Slave Clock stretch maximum cycles 0 8 SR Status Register 0x1C 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 MENB Master Interface Enable 16 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 SRR Slew Rate Register 0x3C 32 read-write n 0x0 0x0 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 THR Transmit Holding Register 0x18 32 write-only n 0x0 0x0 TXDATA Data to Transmit 0 8 TWIM_CMDR Command Register 0xC 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 TWIM_CR Control Register 0x0 32 write-only n 0x0 0x0 MDIS Master Disable 1 1 MEN Master Enable 0 1 SMDIS SMBus Disable 5 1 SMEN SMBus Enable 4 1 STOP Stop the current transfer 8 1 SWRST Software Reset 7 1 TWIM_CWGR Clock Waveform Generator Register 0x4 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 TWIM_HSCWGR HS-mode Clock Waveform Generator 0x38 32 read-write n 0x0 0x0 DATA Data Setup and Hold Cycles 24 4 EXP Clock Prescaler 28 3 HIGH Clock High Cycles 8 8 LOW Clock Low Cycles 0 8 STASTO START and STOP Cycles 16 8 TWIM_HSSRR HS-mode Slew Rate Register 0x40 32 read-write n 0x0 0x0 CLDRIVEH Clock Drive Strength HIGH 20 2 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIM_IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_NCMDR Next Command Register 0x10 32 read-write n 0x0 0x0 ACKLAST ACK Last Master RX Byte 25 1 HS HS-mode 26 1 HSMCODE HS-mode Master Code 28 3 NBYTES Number of data bytes in transfer 16 8 PECEN Packet Error Checking Enable 24 1 READ Transfer Direction 0 1 REPSAME Transfer is to same address as previous address 12 1 SADR Slave Address 1 10 START Send START condition 13 1 STOP Send STOP condition 14 1 TENBIT Ten Bit Addressing Mode 11 1 VALID CMDR Valid 15 1 TWIM_PR Parameter Register 0x30 32 read-only n 0x0 0x0 HS HS-mode 0 1 TWIM_RHR Receive Holding Register 0x14 32 read-only n 0x0 0x0 RXDATA Received Data 0 8 TWIM_SCR Status Clear Register 0x2C 32 write-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 CCOMP Command Complete 3 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 PECERR PEC Error 13 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TWIM_SMBTR SMBus Timing Register 0x8 32 read-write n 0x0 0x0 EXP SMBus Timeout Clock prescaler 28 4 THMAX Clock High maximum cycles 16 8 TLOWM Master Clock stretch maximum cycles 8 8 TLOWS Slave Clock stretch maximum cycles 0 8 TWIM_SR Status Register 0x1C 32 read-only n 0x0 0x0 ANAK NAK in Address Phase Received 8 1 ARBLST Arbitration Lost 10 1 BUSFREE Two-wire Bus is Free 5 1 CCOMP Command Complete 3 1 CRDY Ready for More Commands 2 1 DNAK NAK in Data Phase Received 9 1 HSMCACK ACK in HS-mode Master Code Phase Received 17 1 IDLE Master Interface is Idle 4 1 MENB Master Interface Enable 16 1 PECERR PEC Error 13 1 RXRDY RHR Data Ready 0 1 SMBALERT SMBus Alert 11 1 STOP Stop Request Accepted 14 1 TOUT Timeout 12 1 TXRDY THR Data Ready 1 1 TWIM_SRR Slew Rate Register 0x3C 32 read-write n 0x0 0x0 CLDRIVEL Clock Drive Strength LOW 16 3 CLSLEW Clock Slew Limit 24 2 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIM_THR Transmit Holding Register 0x18 32 write-only n 0x0 0x0 TXDATA Data to Transmit 0 8 TWIM_VR Version Register 0x34 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 VR Version Register 0x34 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12 TWIS0 Two-wire Slave Interface 0 TWIS 0x0 0x0 0x400 registers n TWIS0 62 CR Control Register 0x0 32 read-write n 0x0 0x0 ACK Slave Receiver Data Phase ACK Value 12 1 ADR Slave Address 16 10 BRIDGE Bridge Control Enable 27 1 CUP NBYTES Count Up 13 1 GCMATCH General Call Address Match 3 1 PECEN Packet Error Checking Enable 11 1 SEN Slave Enable 0 1 SMATCH Slave Address Match 2 1 SMBALERT SMBus Alert 8 1 SMDA SMBus Default Address 9 1 SMEN SMBus Mode Enable 1 1 SMHH SMBus Host Header 10 1 SOAM Stretch Clock on Address Match 14 1 SODR Stretch Clock on Data Byte Reception 15 1 STREN Clock Stretch Enable 4 1 SWRST Software Reset 7 1 TENBIT Ten Bit Address Match 26 1 HSSRR HS-mode Slew Rate Register 0x3C 32 read-write n 0x0 0x0 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 HSTR HS-mode Timing Register 0x34 32 read-write n 0x0 0x0 HDDAT Data Hold Cycles 16 8 IDR Interrupt Disable Register 0x20 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 IER Interrupt Enable Register 0x1C 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 IMR Interrupt Mask Register 0x24 32 read-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 NBYTES NBYTES Register 0x4 32 read-write n 0x0 0x0 NBYTES Number of Bytes to Transfer 0 8 PECR Packet Error Check Register 0x14 32 read-only n 0x0 0x0 PEC Calculated PEC Value 0 8 PR Parameter Register 0x2C 32 read-only n 0x0 0x0 HS HS-mode 0 1 read-only RHR Receive Holding Register 0xC 32 read-only n 0x0 0x0 RXDATA Received Data Byte 0 8 SCR Status Clear Register 0x28 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 URUN Underrun 6 1 SR Status Register 0x18 32 read-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SEN Slave Enabled 2 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TRA Transmitter Mode 5 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 SRR Slew Rate Register 0x38 32 read-write n 0x0 0x0 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 THR Transmit Holding Register 0x10 32 write-only n 0x0 0x0 TXDATA Data Byte to Transmit 0 8 TR Timing Register 0x8 32 read-write n 0x0 0x0 EXP Clock Prescaler 28 4 SUDAT Data Setup Cycles 16 8 TLOWS SMBus Tlow:sext Cycles 0 8 TTOUT SMBus Ttimeout Cycles 8 8 TWIS_CR Control Register 0x0 32 read-write n 0x0 0x0 ACK Slave Receiver Data Phase ACK Value 12 1 ADR Slave Address 16 10 BRIDGE Bridge Control Enable 27 1 CUP NBYTES Count Up 13 1 GCMATCH General Call Address Match 3 1 PECEN Packet Error Checking Enable 11 1 SEN Slave Enable 0 1 SMATCH Slave Address Match 2 1 SMBALERT SMBus Alert 8 1 SMDA SMBus Default Address 9 1 SMEN SMBus Mode Enable 1 1 SMHH SMBus Host Header 10 1 SOAM Stretch Clock on Address Match 14 1 SODR Stretch Clock on Data Byte Reception 15 1 STREN Clock Stretch Enable 4 1 SWRST Software Reset 7 1 TENBIT Ten Bit Address Match 26 1 TWIS_HSSRR HS-mode Slew Rate Register 0x3C 32 read-write n 0x0 0x0 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIS_HSTR HS-mode Timing Register 0x34 32 read-write n 0x0 0x0 HDDAT Data Hold Cycles 16 8 TWIS_IDR Interrupt Disable Register 0x20 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 TWIS_IER Interrupt Enable Register 0x1C 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 TWIS_IMR Interrupt Mask Register 0x24 32 read-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 TWIS_NBYTES NBYTES Register 0x4 32 read-write n 0x0 0x0 NBYTES Number of Bytes to Transfer 0 8 TWIS_PECR Packet Error Check Register 0x14 32 read-only n 0x0 0x0 PEC Calculated PEC Value 0 8 TWIS_PR Parameter Register 0x2C 32 read-only n 0x0 0x0 HS HS-mode 0 1 read-only TWIS_RHR Receive Holding Register 0xC 32 read-only n 0x0 0x0 RXDATA Received Data Byte 0 8 TWIS_SCR Status Clear Register 0x28 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 URUN Underrun 6 1 TWIS_SR Status Register 0x18 32 read-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SEN Slave Enabled 2 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TRA Transmitter Mode 5 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 TWIS_SRR Slew Rate Register 0x38 32 read-write n 0x0 0x0 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIS_THR Transmit Holding Register 0x10 32 write-only n 0x0 0x0 TXDATA Data Byte to Transmit 0 8 TWIS_TR Timing Register 0x8 32 read-write n 0x0 0x0 EXP Clock Prescaler 28 4 SUDAT Data Setup Cycles 16 8 TLOWS SMBus Tlow:sext Cycles 0 8 TTOUT SMBus Ttimeout Cycles 8 8 TWIS_VR Version Register 0x30 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 VERSION Version Number 0 12 VR Version Register 0x30 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 VERSION Version Number 0 12 TWIS1 Two-wire Slave Interface 1 TWIS 0x0 0x0 0x400 registers n TWIS1 64 CR Control Register 0x0 32 read-write n 0x0 0x0 ACK Slave Receiver Data Phase ACK Value 12 1 ADR Slave Address 16 10 BRIDGE Bridge Control Enable 27 1 CUP NBYTES Count Up 13 1 GCMATCH General Call Address Match 3 1 PECEN Packet Error Checking Enable 11 1 SEN Slave Enable 0 1 SMATCH Slave Address Match 2 1 SMBALERT SMBus Alert 8 1 SMDA SMBus Default Address 9 1 SMEN SMBus Mode Enable 1 1 SMHH SMBus Host Header 10 1 SOAM Stretch Clock on Address Match 14 1 SODR Stretch Clock on Data Byte Reception 15 1 STREN Clock Stretch Enable 4 1 SWRST Software Reset 7 1 TENBIT Ten Bit Address Match 26 1 HSSRR HS-mode Slew Rate Register 0x3C 32 read-write n 0x0 0x0 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 HSTR HS-mode Timing Register 0x34 32 read-write n 0x0 0x0 HDDAT Data Hold Cycles 16 8 IDR Interrupt Disable Register 0x20 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 IER Interrupt Enable Register 0x1C 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 IMR Interrupt Mask Register 0x24 32 read-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 NBYTES NBYTES Register 0x4 32 read-write n 0x0 0x0 NBYTES Number of Bytes to Transfer 0 8 PECR Packet Error Check Register 0x14 32 read-only n 0x0 0x0 PEC Calculated PEC Value 0 8 PR Parameter Register 0x2C 32 read-only n 0x0 0x0 HS HS-mode 0 1 read-only RHR Receive Holding Register 0xC 32 read-only n 0x0 0x0 RXDATA Received Data Byte 0 8 SCR Status Clear Register 0x28 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 URUN Underrun 6 1 SR Status Register 0x18 32 read-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SEN Slave Enabled 2 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TRA Transmitter Mode 5 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 SRR Slew Rate Register 0x38 32 read-write n 0x0 0x0 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 THR Transmit Holding Register 0x10 32 write-only n 0x0 0x0 TXDATA Data Byte to Transmit 0 8 TR Timing Register 0x8 32 read-write n 0x0 0x0 EXP Clock Prescaler 28 4 SUDAT Data Setup Cycles 16 8 TLOWS SMBus Tlow:sext Cycles 0 8 TTOUT SMBus Ttimeout Cycles 8 8 TWIS_CR Control Register 0x0 32 read-write n 0x0 0x0 ACK Slave Receiver Data Phase ACK Value 12 1 ADR Slave Address 16 10 BRIDGE Bridge Control Enable 27 1 CUP NBYTES Count Up 13 1 GCMATCH General Call Address Match 3 1 PECEN Packet Error Checking Enable 11 1 SEN Slave Enable 0 1 SMATCH Slave Address Match 2 1 SMBALERT SMBus Alert 8 1 SMDA SMBus Default Address 9 1 SMEN SMBus Mode Enable 1 1 SMHH SMBus Host Header 10 1 SOAM Stretch Clock on Address Match 14 1 SODR Stretch Clock on Data Byte Reception 15 1 STREN Clock Stretch Enable 4 1 SWRST Software Reset 7 1 TENBIT Ten Bit Address Match 26 1 TWIS_HSSRR HS-mode Slew Rate Register 0x3C 32 read-write n 0x0 0x0 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIS_HSTR HS-mode Timing Register 0x34 32 read-write n 0x0 0x0 HDDAT Data Hold Cycles 16 8 TWIS_IDR Interrupt Disable Register 0x20 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 TWIS_IER Interrupt Enable Register 0x1C 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 TWIS_IMR Interrupt Mask Register 0x24 32 read-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 TWIS_NBYTES NBYTES Register 0x4 32 read-write n 0x0 0x0 NBYTES Number of Bytes to Transfer 0 8 TWIS_PECR Packet Error Check Register 0x14 32 read-only n 0x0 0x0 PEC Calculated PEC Value 0 8 TWIS_PR Parameter Register 0x2C 32 read-only n 0x0 0x0 HS HS-mode 0 1 read-only TWIS_RHR Receive Holding Register 0xC 32 read-only n 0x0 0x0 RXDATA Received Data Byte 0 8 TWIS_SCR Status Clear Register 0x28 32 write-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 SAM Slave Address Match 16 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 URUN Underrun 6 1 TWIS_SR Status Register 0x18 32 read-only n 0x0 0x0 BTF Byte Transfer Finished 23 1 BUSERR Bus Error 14 1 GCM General Call Match 17 1 NAK NAK Received 8 1 ORUN Overrun 7 1 REP Repeated Start Received 22 1 RXRDY RX Buffer Ready 0 1 SAM Slave Address Match 16 1 SEN Slave Enabled 2 1 SMBALERTM SMBus Alert Response Address Match 18 1 SMBDAM SMBus Default Address Match 20 1 SMBHHM SMBus Host Header Address Match 19 1 SMBPECERR SMBus PEC Error 13 1 SMBTOUT SMBus Timeout 12 1 STO Stop Received 21 1 TCOMP Transmission Complete 3 1 TRA Transmitter Mode 5 1 TXRDY TX Buffer Ready 1 1 URUN Underrun 6 1 TWIS_SRR Slew Rate Register 0x38 32 read-write n 0x0 0x0 DADRIVEL Data Drive Strength LOW 0 3 DASLEW Data Slew Limit 8 2 FILTER Input Spike Filter Control 28 2 TWIS_THR Transmit Holding Register 0x10 32 write-only n 0x0 0x0 TXDATA Data Byte to Transmit 0 8 TWIS_TR Timing Register 0x8 32 read-write n 0x0 0x0 EXP Clock Prescaler 28 4 SUDAT Data Setup Cycles 16 8 TLOWS SMBus Tlow:sext Cycles 0 8 TTOUT SMBus Ttimeout Cycles 8 8 TWIS_VR Version Register 0x30 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 VERSION Version Number 0 12 VR Version Register 0x30 32 read-only n 0x0 0x0 VARIANT Variant Number 16 4 VERSION Version Number 0 12 USART0 Universal Synchronous Asynchronous Receiver Transmitter 0 USART 0x0 0x0 0x400 registers n USART0 65 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CDSelect DISABLE Disables the clock 0x0 BYPASS Clock Divisor Bypass 0x1 2 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD) Baud Rate (Synchronous Mode) = Selected Clock/CD 0x2 FP Fractional Part 16 3 FPSelect 0 Fractional divider is disabled 0x0 CR Control Register 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 FCS Force SPI Chip Select 18 1 FCSSelect 0 No effect 0x0 1 Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer) 0x1 LINABT Abort the current LIN transmission 20 1 LINWKUP Sends a wakeup signal on the LIN bus 21 1 RCS Release SPI Chip Select 19 1 RCSSelect 0 No effect 0x0 1 Releases the Slave Select Line NSS (RTS pin) 0x1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RTSDIS Request to Send Disable 19 1 RTSDISSelect 0 No effect 0x0 1 Drives the pin RTS to 1 0x1 RTSEN Request to Send Enable 18 1 RTSENSelect 0 No effect 0x0 1 Drives the pin RTS to 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 CTSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 ITER Max number of Repetitions Reached 10 1 ITERSelect 0 Maximum number of repetitions has not been reached since the last RSIT 0x0 1 Maximum number of repetitions has been reached since the last RSIT 0x1 LINBE LIN Bit Error 25 1 LINBLS LIN Bus Line Status 23 1 LINBLSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 LINCE LIN Checksum Error 28 1 LINHTE LIN Header Timeout Error 31 1 LINHTESelect 0 COMM_RX is at 0 0x0 1 COMM_RX is at 1 0x1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINIPE LIN Identifier Parity Error 27 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINSNRE LIN Slave Not Responding Error 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINSTESelect 0 COMM_TX is at 0 0x0 1 COMM_TX is at 1 0x1 LINTC LIN Transfer Conpleted 15 1 MANERR Manchester Error 24 1 MANERRSelect 0 No Manchester error has been detected since the last RSTSTA 0x0 1 At least one Manchester error has been detected since the last RSTSTA 0x1 NACK Non Acknowledge 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 UNRE SPI Underrun Error 10 1 UNRESelect 0 No SPI underrun error has occurred since the last RSTSTA 0x0 1 At least one SPI underrun error has occurred since the last RSTSTA 0x1 FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 FI_DI_RATIOSelect DISABLE Baud Rate = 0 0x0 IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 ITER Iteration Interrupt Disable 10 1 ITERSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINBE LIN Bus Error Interrupt Disable 25 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINHTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINSTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Disable 15 1 MANE Manchester Error Interrupt Disable 20 1 MANEA Manchester Error Interrupt Disable 24 1 MANEASelect 0 No effect 0x0 1 Disables the corresponding interrupt 0x1 NACK Non Acknowledge Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 UNRE SPI Underrun Error Interrupt Disable 10 1 UNRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 ITER Iteration Interrupt Enable 10 1 ITERSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINBE LIN Bus Error Interrupt Enable 25 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINHTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINSTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Enable 15 1 MANE Manchester Error Interrupt Enable 20 1 MANEA Manchester Error Interrupt Enable 24 1 MANEASelect 0 No effect 0x0 1 Enables the interrupt 0x1 NACK Non Acknowledge Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 UNRE SPI Underrun Error Interrupt Enable 10 1 UNRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 IFR IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER Irda filter 0 8 IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 ITER Iteration Interrupt Mask 10 1 ITERSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBE LIN Bus Error Interrupt Mask 25 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINHTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINID LIN Identifier Sent or LIN Received Interrupt Mask 14 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINSTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINTC LIN Transfer Conpleted Interrupt Mask 15 1 MANE Manchester Error Interrupt Mask 20 1 MANEA Manchester Error Interrupt Mask 24 1 MANEASelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 NACK Non Acknowledge Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 UNRE SPI Underrun Error Interrupt Mask 10 1 UNRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The LIN Controller transmits the response 0x0 SUBSCRIBE The LIN Controller receives the response 0x1 IGNORE The LIN Controller doesn't transmit and doesn't receive the response 0x2 PARDIS Parity Disable 2 1 PDCM PDC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift compensation 30 1 DRIFTSelect 0 The USART can not recover from an important clock drift 0x0 1 The USART can recover from clock drift. The 16X clock mode must be enabled 0x1 RX_MPOL Receiver Manchester Polarity 28 1 RX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 RX_PL Receiver Preamble Length 16 4 RX_PLSelect 0 The receiver preamble pattern detection is disabled 0x0 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 TX_PL Transmitter Preamble Length 0 4 TX_PLSelect 0 The Transmitter Preamble pattern generation is disabled 0x0 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal Mode 0x0 ECHO Automatic Echo. Receiver input is connected to the TXD pin 0x1 LOCAL_LOOP Local Loopback. Transmitter output is connected to the Receiver Input 0x2 REMOTE_LOOP Remote Loopback. RXD pin is internally connected to the TXD pin 0x3 CHRL Character Length. 6 2 CHRLSelect 5 5 bits 0x0 6 6 bits 0x1 7 7 bits 0x2 8 8 bits 0x3 CLKO Clock Output Select 18 1 CLKOSelect 0 The USART does not drive the SCK pin 0x0 1 The USART drives the SCK pin if USCLKS does not select the external clock SCK 0x1 CPHA SPI CLock Phase 8 1 CPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK 0x1 CPOL SPI Clock Polarity 16 1 CPOLSelect ZERO The inactive state value of SPCK is logic level zero 0x0 ONE The inactive state value of SPCK is logic level one 0x1 DSNACK Disable Successive NACK 21 1 DSNACKSelect 0 NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) 0x0 1 Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted 0x1 FILTER Infrared Receive Line Filter 28 1 FILTERSelect 0 The USART does not filter the receive line 0x0 1 The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) 0x1 INACK Inhibit Non Acknowledge 20 1 INACKSelect 0 The NACK is generated 0x0 1 The NACK is not generated 0x1 INVDATA Inverted data 23 1 MAN Manchester Encoder/Decoder Enable 29 1 MANSelect 0 Manchester Encoder/Decoder is disabled 0x0 1 Manchester Encoder/Decoder is enabled 0x1 MAX_ITERATION Max interation 24 3 MODE Usart Mode 0 4 MODESelect NORMAL Normal 0x0 RS485 RS485 0x1 HARDWARE Hardware Handshaking 0x2 MODEM Modem 0x3 ISO7816_T0 IS07816 Protocol: T = 0 0x4 ISO7816_T1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_Master LIN Master 0xa LIN_Slave LIN Slave 0xb SPI_Master SPI Master 0xe SPI_Slave SPI Slave 0xf MODE9 9-bit Character Length 17 1 MODE9Select 0 CHRL defines character length 0x0 1 9-bit character length 0x1 MODSYNC Manchester Synchronization Mode 30 1 MODSYNCSelect 0 The Manchester Start bit is a 0 to 1 transition 0x0 1 The Manchester Start bit is a 1 to 0 transition 0x1 MSBF Bit Order 16 1 MSBFSelect LSBF Least Significant Bit first 0x0 MSBF Most Significant Bit first 0x1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect 1 1 stop bit 0x0 1_5 1.5 stop bits (Only valid if SYNC=0) 0x1 2 2 stop bits 0x2 ONEBIT Start Frame Delimiter selector 31 1 ONEBITSelect 0 Start Frame delimiter is COMMAND or DATA SYNC 0x0 1 Start Frame delimiter is One Bit 0x1 OVER Oversampling Mode 19 1 OVERSelect X16 16x Oversampling 0x0 X8 8x Oversampling 0x1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NONE No Parity 0x4 5 No Parity 0x5 MULTI Multi-drop mode 0x6 7 Multi-drop mode 0x7 SYNC Synchronous Mode Select 8 1 SYNCSelect 0 USART operates in Synchronous Mode 0x0 1 USART operates in Asynchronous Mode 0x1 USCLKS Clock Selection 4 2 USCLKSSelect MCK MCK 0x0 MCK_DIV MCK / DIV 0x1 SCK SCK 0x3 VAR_SYNC Variable synchronization of command/data sync Start Frame Delimiter 22 1 VAR_SYNCSelect 0 User defined configuration of command or data sync field depending on SYNC value 0x0 1 The sync field is updated when a character is written into THR register 0x1 NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Error number during ISO7816 transfers 0 8 RHR Receiver Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 RXSYNHSelect 0 Last character received is a Data 0x0 1 Last character received is a Command 0x1 RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 TOSelect DISABLE Disables the RX Time-out function 0x0 THR Transmitter Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be transmitted 15 1 TXSYNHSelect 0 The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC 0x0 1 The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC 0x1 TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 TGSelect DISABLE Disables the TX Timeguard function. 0x0 USART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CDSelect DISABLE Disables the clock 0x0 BYPASS Clock Divisor Bypass 0x1 2 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD); Baud Rate (Synchronous Mode) = Selected Clock/CD; 0x2 FP Fractional Part 16 3 FPSelect 0 Fractional divider is disabled 0x0 USART_CR Control Register LIN_MODE 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 LINABT Abort the current LIN transmission 20 1 LINWKUP Sends a wakeup signal on the LIN bus 21 1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RTSDIS Request to Send Disable 19 1 RTSDISSelect 0 No effect 0x0 1 Drives the pin RTS to 1 0x1 RTSEN Request to Send Enable 18 1 RTSENSelect 0 No effect 0x0 1 Drives the pin RTS to 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 USART_CSR Channel Status Register LIN_MODE 0x14 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 ITER Max number of Repetitions Reached 10 1 ITERSelect 0 Maximum number of repetitions has not been reached since the last RSIT 0x0 1 Maximum number of repetitions has been reached since the last RSIT 0x1 LINBE LIN Bit Error 25 1 LINBLS LIN Bus Line Status 23 1 LINBLSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 LINCE LIN Checksum Error 28 1 LINHTE LIN Header Timeout Error 31 1 LINHTESelect 0 COMM_RX is at 0 0x0 1 COMM_RX is at 1 0x1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINIPE LIN Identifier Parity Error 27 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINSNRE LIN Slave Not Responding Error 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINSTESelect 0 COMM_TX is at 0 0x0 1 COMM_TX is at 1 0x1 LINTC LIN Transfer Conpleted 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 USART_FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 FI_DI_RATIOSelect DISABLE Baud Rate = 0 0x0 USART_IDR Interrupt Disable Register LIN_MODE 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 ITER Iteration Interrupt Disable 10 1 ITERSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINBE LIN Bus Error Interrupt Disable 25 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINHTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINSTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Disable 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 USART_IER Interrupt Enable Register LIN_MODE 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 ITER Iteration Interrupt Enable 10 1 ITERSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINBE LIN Bus Error Interrupt Enable 25 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINHTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINSTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Enable 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 USART_IFR IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER Irda filter 0 8 USART_IMR Interrupt Mask Register LIN_MODE 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 ITER Iteration Interrupt Mask 10 1 ITERSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBE LIN Bus Error Interrupt Mask 25 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINHTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINID LIN Identifier Sent or LIN Received Interrupt Mask 14 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINSTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINTC LIN Transfer Conpleted Interrupt Mask 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 USART_LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 USART_LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 USART_LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The LIN Controller transmits the response 0x0 SUBSCRIBE The LIN Controller receives the response 0x1 IGNORE The LIN Controller doesn't transmit and doesn't receive the response 0x2 PARDIS Parity Disable 2 1 PDCM PDC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 USART_MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift compensation 30 1 DRIFTSelect 0 The USART can not recover from an important clock drift 0x0 1 The USART can recover from clock drift. The 16X clock mode must be enabled 0x1 RX_MPOL Receiver Manchester Polarity 28 1 RX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 RX_PL Receiver Preamble Length 16 4 RX_PLSelect 0 The receiver preamble pattern detection is disabled 0x0 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 TX_PL Transmitter Preamble Length 0 4 TX_PLSelect 0 The Transmitter Preamble pattern generation is disabled 0x0 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 USART_MR Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal Mode 0x0 ECHO Automatic Echo. Receiver input is connected to the TXD pin 0x1 LOCAL_LOOP Local Loopback. Transmitter output is connected to the Receiver Input 0x2 REMOTE_LOOP Remote Loopback. RXD pin is internally connected to the TXD pin 0x3 CHRL Character Length. 6 2 CHRLSelect 5 5 bits 0x0 6 6 bits 0x1 7 7 bits 0x2 8 8 bits 0x3 CLKO Clock Output Select 18 1 CLKOSelect 0 The USART does not drive the SCK pin 0x0 1 The USART drives the SCK pin if USCLKS does not select the external clock SCK 0x1 CPHA SPI CLock Phase 8 1 CPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK 0x1 CPOL SPI Clock Polarity 16 1 CPOLSelect ZERO The inactive state value of SPCK is logic level zero 0x0 ONE The inactive state value of SPCK is logic level one 0x1 DSNACK Disable Successive NACK 21 1 DSNACKSelect 0 NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) 0x0 1 Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted 0x1 FILTER Infrared Receive Line Filter 28 1 FILTERSelect 0 The USART does not filter the receive line 0x0 1 The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) 0x1 INACK Inhibit Non Acknowledge 20 1 INACKSelect 0 The NACK is generated 0x0 1 The NACK is not generated 0x1 INVDATA Inverted data 23 1 MAX_ITERATION Max interation 24 3 MODE Usart Mode 0 4 MODESelect NORMAL Normal 0x0 RS485 RS485 0x1 HARDWARE Hardware Handshaking 0x2 MODEM Modem 0x3 ISO7816_T0 IS07816 Protocol: T = 0 0x4 ISO7816_T1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_Master LIN Master 0xa LIN_Slave LIN Slave 0xb SPI_Master SPI Master 0xe SPI_Slave SPI Slave 0xf MODE9 9-bit Character Length 17 1 MODE9Select 0 CHRL defines character length 0x0 1 9-bit character length 0x1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect 1 1 stop bit 0x0 1_5 1.5 stop bits (Only valid if SYNC=0) 0x1 2 2 stop bits 0x2 OVER Oversampling Mode 19 1 OVERSelect X16 16x Oversampling 0x0 X8 8x Oversampling 0x1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NONE No Parity 0x4 5 No Parity 0x5 MULTI Multi-drop mode 0x6 7 Multi-drop mode 0x7 USCLKS Clock Selection 4 2 USCLKSSelect MCK MCK 0x0 MCK_DIV MCK / DIV 0x1 SCK SCK 0x3 USART_NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Error number during ISO7816 transfers 0 8 USART_RHR Receiver Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 RXSYNHSelect 0 Last character received is a Data 0x0 1 Last character received is a Command 0x1 USART_RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 TOSelect DISABLE Disables the RX Time-out function 0x0 USART_THR Transmitter Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be transmitted 15 1 TXSYNHSelect 0 The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC 0x0 1 The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC 0x1 USART_TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 TGSelect DISABLE Disables the TX Timeguard function. 0x0 USART_VERSION Version Register 0xFC 32 read-only n 0x0 0x0 MFN MFN 16 4 VERSION Version 0 12 USART_WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPENSelect 0 Disables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) 0x0 1 Enables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) 0x1 WPKEY Write Protect Key 8 24 USART_WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPV Write Protect Violation Status 0 1 WPVSelect 0 No Write Protect Violation has occurred since the last read of the WPSR register 0x0 1 A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC 0x1 WPVSRC Write Protect Violation Source 8 16 VERSION Version Register 0xFC 32 read-only n 0x0 0x0 MFN MFN 16 4 VERSION Version 0 12 WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPENSelect 0 Disables the Write Protect if WPKEY corresponds to 0x858365 ( USA in ACII) 0x0 1 Enables the Write Protect if WPKEY corresponds to 0x858365 ( USA in ACII) 0x1 WPKEY Write Protect Key 8 24 WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPV Write Protect Violation Status 0 1 WPVSelect 0 No Write Protect Violation has occurred since the last read of the WPSR register 0x0 1 A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC 0x1 WPVSRC Write Protect Violation Source 8 16 USART1 Universal Synchronous Asynchronous Receiver Transmitter 1 USART 0x0 0x0 0x400 registers n USART1 66 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CDSelect DISABLE Disables the clock 0x0 BYPASS Clock Divisor Bypass 0x1 2 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD) Baud Rate (Synchronous Mode) = Selected Clock/CD 0x2 FP Fractional Part 16 3 FPSelect 0 Fractional divider is disabled 0x0 CR Control Register 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 FCS Force SPI Chip Select 18 1 FCSSelect 0 No effect 0x0 1 Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer) 0x1 LINABT Abort the current LIN transmission 20 1 LINWKUP Sends a wakeup signal on the LIN bus 21 1 RCS Release SPI Chip Select 19 1 RCSSelect 0 No effect 0x0 1 Releases the Slave Select Line NSS (RTS pin) 0x1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RTSDIS Request to Send Disable 19 1 RTSDISSelect 0 No effect 0x0 1 Drives the pin RTS to 1 0x1 RTSEN Request to Send Enable 18 1 RTSENSelect 0 No effect 0x0 1 Drives the pin RTS to 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 CTSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 ITER Max number of Repetitions Reached 10 1 ITERSelect 0 Maximum number of repetitions has not been reached since the last RSIT 0x0 1 Maximum number of repetitions has been reached since the last RSIT 0x1 LINBE LIN Bit Error 25 1 LINBLS LIN Bus Line Status 23 1 LINBLSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 LINCE LIN Checksum Error 28 1 LINHTE LIN Header Timeout Error 31 1 LINHTESelect 0 COMM_RX is at 0 0x0 1 COMM_RX is at 1 0x1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINIPE LIN Identifier Parity Error 27 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINSNRE LIN Slave Not Responding Error 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINSTESelect 0 COMM_TX is at 0 0x0 1 COMM_TX is at 1 0x1 LINTC LIN Transfer Conpleted 15 1 MANERR Manchester Error 24 1 MANERRSelect 0 No Manchester error has been detected since the last RSTSTA 0x0 1 At least one Manchester error has been detected since the last RSTSTA 0x1 NACK Non Acknowledge 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 UNRE SPI Underrun Error 10 1 UNRESelect 0 No SPI underrun error has occurred since the last RSTSTA 0x0 1 At least one SPI underrun error has occurred since the last RSTSTA 0x1 FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 FI_DI_RATIOSelect DISABLE Baud Rate = 0 0x0 IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 ITER Iteration Interrupt Disable 10 1 ITERSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINBE LIN Bus Error Interrupt Disable 25 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINHTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINSTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Disable 15 1 MANE Manchester Error Interrupt Disable 20 1 MANEA Manchester Error Interrupt Disable 24 1 MANEASelect 0 No effect 0x0 1 Disables the corresponding interrupt 0x1 NACK Non Acknowledge Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 UNRE SPI Underrun Error Interrupt Disable 10 1 UNRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 ITER Iteration Interrupt Enable 10 1 ITERSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINBE LIN Bus Error Interrupt Enable 25 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINHTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINSTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Enable 15 1 MANE Manchester Error Interrupt Enable 20 1 MANEA Manchester Error Interrupt Enable 24 1 MANEASelect 0 No effect 0x0 1 Enables the interrupt 0x1 NACK Non Acknowledge Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 UNRE SPI Underrun Error Interrupt Enable 10 1 UNRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 IFR IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER Irda filter 0 8 IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 ITER Iteration Interrupt Mask 10 1 ITERSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBE LIN Bus Error Interrupt Mask 25 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINHTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINID LIN Identifier Sent or LIN Received Interrupt Mask 14 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINSTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINTC LIN Transfer Conpleted Interrupt Mask 15 1 MANE Manchester Error Interrupt Mask 20 1 MANEA Manchester Error Interrupt Mask 24 1 MANEASelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 NACK Non Acknowledge Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 UNRE SPI Underrun Error Interrupt Mask 10 1 UNRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The LIN Controller transmits the response 0x0 SUBSCRIBE The LIN Controller receives the response 0x1 IGNORE The LIN Controller doesn't transmit and doesn't receive the response 0x2 PARDIS Parity Disable 2 1 PDCM PDC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift compensation 30 1 DRIFTSelect 0 The USART can not recover from an important clock drift 0x0 1 The USART can recover from clock drift. The 16X clock mode must be enabled 0x1 RX_MPOL Receiver Manchester Polarity 28 1 RX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 RX_PL Receiver Preamble Length 16 4 RX_PLSelect 0 The receiver preamble pattern detection is disabled 0x0 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 TX_PL Transmitter Preamble Length 0 4 TX_PLSelect 0 The Transmitter Preamble pattern generation is disabled 0x0 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal Mode 0x0 ECHO Automatic Echo. Receiver input is connected to the TXD pin 0x1 LOCAL_LOOP Local Loopback. Transmitter output is connected to the Receiver Input 0x2 REMOTE_LOOP Remote Loopback. RXD pin is internally connected to the TXD pin 0x3 CHRL Character Length. 6 2 CHRLSelect 5 5 bits 0x0 6 6 bits 0x1 7 7 bits 0x2 8 8 bits 0x3 CLKO Clock Output Select 18 1 CLKOSelect 0 The USART does not drive the SCK pin 0x0 1 The USART drives the SCK pin if USCLKS does not select the external clock SCK 0x1 CPHA SPI CLock Phase 8 1 CPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK 0x1 CPOL SPI Clock Polarity 16 1 CPOLSelect ZERO The inactive state value of SPCK is logic level zero 0x0 ONE The inactive state value of SPCK is logic level one 0x1 DSNACK Disable Successive NACK 21 1 DSNACKSelect 0 NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) 0x0 1 Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted 0x1 FILTER Infrared Receive Line Filter 28 1 FILTERSelect 0 The USART does not filter the receive line 0x0 1 The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) 0x1 INACK Inhibit Non Acknowledge 20 1 INACKSelect 0 The NACK is generated 0x0 1 The NACK is not generated 0x1 INVDATA Inverted data 23 1 MAN Manchester Encoder/Decoder Enable 29 1 MANSelect 0 Manchester Encoder/Decoder is disabled 0x0 1 Manchester Encoder/Decoder is enabled 0x1 MAX_ITERATION Max interation 24 3 MODE Usart Mode 0 4 MODESelect NORMAL Normal 0x0 RS485 RS485 0x1 HARDWARE Hardware Handshaking 0x2 MODEM Modem 0x3 ISO7816_T0 IS07816 Protocol: T = 0 0x4 ISO7816_T1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_Master LIN Master 0xa LIN_Slave LIN Slave 0xb SPI_Master SPI Master 0xe SPI_Slave SPI Slave 0xf MODE9 9-bit Character Length 17 1 MODE9Select 0 CHRL defines character length 0x0 1 9-bit character length 0x1 MODSYNC Manchester Synchronization Mode 30 1 MODSYNCSelect 0 The Manchester Start bit is a 0 to 1 transition 0x0 1 The Manchester Start bit is a 1 to 0 transition 0x1 MSBF Bit Order 16 1 MSBFSelect LSBF Least Significant Bit first 0x0 MSBF Most Significant Bit first 0x1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect 1 1 stop bit 0x0 1_5 1.5 stop bits (Only valid if SYNC=0) 0x1 2 2 stop bits 0x2 ONEBIT Start Frame Delimiter selector 31 1 ONEBITSelect 0 Start Frame delimiter is COMMAND or DATA SYNC 0x0 1 Start Frame delimiter is One Bit 0x1 OVER Oversampling Mode 19 1 OVERSelect X16 16x Oversampling 0x0 X8 8x Oversampling 0x1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NONE No Parity 0x4 5 No Parity 0x5 MULTI Multi-drop mode 0x6 7 Multi-drop mode 0x7 SYNC Synchronous Mode Select 8 1 SYNCSelect 0 USART operates in Synchronous Mode 0x0 1 USART operates in Asynchronous Mode 0x1 USCLKS Clock Selection 4 2 USCLKSSelect MCK MCK 0x0 MCK_DIV MCK / DIV 0x1 SCK SCK 0x3 VAR_SYNC Variable synchronization of command/data sync Start Frame Delimiter 22 1 VAR_SYNCSelect 0 User defined configuration of command or data sync field depending on SYNC value 0x0 1 The sync field is updated when a character is written into THR register 0x1 NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Error number during ISO7816 transfers 0 8 RHR Receiver Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 RXSYNHSelect 0 Last character received is a Data 0x0 1 Last character received is a Command 0x1 RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 TOSelect DISABLE Disables the RX Time-out function 0x0 THR Transmitter Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be transmitted 15 1 TXSYNHSelect 0 The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC 0x0 1 The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC 0x1 TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 TGSelect DISABLE Disables the TX Timeguard function. 0x0 USART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CDSelect DISABLE Disables the clock 0x0 BYPASS Clock Divisor Bypass 0x1 2 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD); Baud Rate (Synchronous Mode) = Selected Clock/CD; 0x2 FP Fractional Part 16 3 FPSelect 0 Fractional divider is disabled 0x0 USART_CR Control Register LIN_MODE 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 LINABT Abort the current LIN transmission 20 1 LINWKUP Sends a wakeup signal on the LIN bus 21 1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RTSDIS Request to Send Disable 19 1 RTSDISSelect 0 No effect 0x0 1 Drives the pin RTS to 1 0x1 RTSEN Request to Send Enable 18 1 RTSENSelect 0 No effect 0x0 1 Drives the pin RTS to 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 USART_CSR Channel Status Register LIN_MODE 0x14 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 ITER Max number of Repetitions Reached 10 1 ITERSelect 0 Maximum number of repetitions has not been reached since the last RSIT 0x0 1 Maximum number of repetitions has been reached since the last RSIT 0x1 LINBE LIN Bit Error 25 1 LINBLS LIN Bus Line Status 23 1 LINBLSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 LINCE LIN Checksum Error 28 1 LINHTE LIN Header Timeout Error 31 1 LINHTESelect 0 COMM_RX is at 0 0x0 1 COMM_RX is at 1 0x1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINIPE LIN Identifier Parity Error 27 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINSNRE LIN Slave Not Responding Error 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINSTESelect 0 COMM_TX is at 0 0x0 1 COMM_TX is at 1 0x1 LINTC LIN Transfer Conpleted 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 USART_FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 FI_DI_RATIOSelect DISABLE Baud Rate = 0 0x0 USART_IDR Interrupt Disable Register LIN_MODE 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 ITER Iteration Interrupt Disable 10 1 ITERSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINBE LIN Bus Error Interrupt Disable 25 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINHTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINSTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Disable 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 USART_IER Interrupt Enable Register LIN_MODE 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 ITER Iteration Interrupt Enable 10 1 ITERSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINBE LIN Bus Error Interrupt Enable 25 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINHTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINSTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Enable 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 USART_IFR IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER Irda filter 0 8 USART_IMR Interrupt Mask Register LIN_MODE 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 ITER Iteration Interrupt Mask 10 1 ITERSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBE LIN Bus Error Interrupt Mask 25 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINHTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINID LIN Identifier Sent or LIN Received Interrupt Mask 14 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINSTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINTC LIN Transfer Conpleted Interrupt Mask 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 USART_LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 USART_LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 USART_LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The LIN Controller transmits the response 0x0 SUBSCRIBE The LIN Controller receives the response 0x1 IGNORE The LIN Controller doesn't transmit and doesn't receive the response 0x2 PARDIS Parity Disable 2 1 PDCM PDC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 USART_MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift compensation 30 1 DRIFTSelect 0 The USART can not recover from an important clock drift 0x0 1 The USART can recover from clock drift. The 16X clock mode must be enabled 0x1 RX_MPOL Receiver Manchester Polarity 28 1 RX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 RX_PL Receiver Preamble Length 16 4 RX_PLSelect 0 The receiver preamble pattern detection is disabled 0x0 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 TX_PL Transmitter Preamble Length 0 4 TX_PLSelect 0 The Transmitter Preamble pattern generation is disabled 0x0 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 USART_MR Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal Mode 0x0 ECHO Automatic Echo. Receiver input is connected to the TXD pin 0x1 LOCAL_LOOP Local Loopback. Transmitter output is connected to the Receiver Input 0x2 REMOTE_LOOP Remote Loopback. RXD pin is internally connected to the TXD pin 0x3 CHRL Character Length. 6 2 CHRLSelect 5 5 bits 0x0 6 6 bits 0x1 7 7 bits 0x2 8 8 bits 0x3 CLKO Clock Output Select 18 1 CLKOSelect 0 The USART does not drive the SCK pin 0x0 1 The USART drives the SCK pin if USCLKS does not select the external clock SCK 0x1 CPHA SPI CLock Phase 8 1 CPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK 0x1 CPOL SPI Clock Polarity 16 1 CPOLSelect ZERO The inactive state value of SPCK is logic level zero 0x0 ONE The inactive state value of SPCK is logic level one 0x1 DSNACK Disable Successive NACK 21 1 DSNACKSelect 0 NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) 0x0 1 Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted 0x1 FILTER Infrared Receive Line Filter 28 1 FILTERSelect 0 The USART does not filter the receive line 0x0 1 The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) 0x1 INACK Inhibit Non Acknowledge 20 1 INACKSelect 0 The NACK is generated 0x0 1 The NACK is not generated 0x1 INVDATA Inverted data 23 1 MAX_ITERATION Max interation 24 3 MODE Usart Mode 0 4 MODESelect NORMAL Normal 0x0 RS485 RS485 0x1 HARDWARE Hardware Handshaking 0x2 MODEM Modem 0x3 ISO7816_T0 IS07816 Protocol: T = 0 0x4 ISO7816_T1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_Master LIN Master 0xa LIN_Slave LIN Slave 0xb SPI_Master SPI Master 0xe SPI_Slave SPI Slave 0xf MODE9 9-bit Character Length 17 1 MODE9Select 0 CHRL defines character length 0x0 1 9-bit character length 0x1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect 1 1 stop bit 0x0 1_5 1.5 stop bits (Only valid if SYNC=0) 0x1 2 2 stop bits 0x2 OVER Oversampling Mode 19 1 OVERSelect X16 16x Oversampling 0x0 X8 8x Oversampling 0x1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NONE No Parity 0x4 5 No Parity 0x5 MULTI Multi-drop mode 0x6 7 Multi-drop mode 0x7 USCLKS Clock Selection 4 2 USCLKSSelect MCK MCK 0x0 MCK_DIV MCK / DIV 0x1 SCK SCK 0x3 USART_NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Error number during ISO7816 transfers 0 8 USART_RHR Receiver Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 RXSYNHSelect 0 Last character received is a Data 0x0 1 Last character received is a Command 0x1 USART_RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 TOSelect DISABLE Disables the RX Time-out function 0x0 USART_THR Transmitter Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be transmitted 15 1 TXSYNHSelect 0 The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC 0x0 1 The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC 0x1 USART_TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 TGSelect DISABLE Disables the TX Timeguard function. 0x0 USART_VERSION Version Register 0xFC 32 read-only n 0x0 0x0 MFN MFN 16 4 VERSION Version 0 12 USART_WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPENSelect 0 Disables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) 0x0 1 Enables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) 0x1 WPKEY Write Protect Key 8 24 USART_WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPV Write Protect Violation Status 0 1 WPVSelect 0 No Write Protect Violation has occurred since the last read of the WPSR register 0x0 1 A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC 0x1 WPVSRC Write Protect Violation Source 8 16 VERSION Version Register 0xFC 32 read-only n 0x0 0x0 MFN MFN 16 4 VERSION Version 0 12 WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPENSelect 0 Disables the Write Protect if WPKEY corresponds to 0x858365 ( USA in ACII) 0x0 1 Enables the Write Protect if WPKEY corresponds to 0x858365 ( USA in ACII) 0x1 WPKEY Write Protect Key 8 24 WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPV Write Protect Violation Status 0 1 WPVSelect 0 No Write Protect Violation has occurred since the last read of the WPSR register 0x0 1 A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC 0x1 WPVSRC Write Protect Violation Source 8 16 USART2 Universal Synchronous Asynchronous Receiver Transmitter 2 USART 0x0 0x0 0x400 registers n USART2 67 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CDSelect DISABLE Disables the clock 0x0 BYPASS Clock Divisor Bypass 0x1 2 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD) Baud Rate (Synchronous Mode) = Selected Clock/CD 0x2 FP Fractional Part 16 3 FPSelect 0 Fractional divider is disabled 0x0 CR Control Register 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 FCS Force SPI Chip Select 18 1 FCSSelect 0 No effect 0x0 1 Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer) 0x1 LINABT Abort the current LIN transmission 20 1 LINWKUP Sends a wakeup signal on the LIN bus 21 1 RCS Release SPI Chip Select 19 1 RCSSelect 0 No effect 0x0 1 Releases the Slave Select Line NSS (RTS pin) 0x1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RTSDIS Request to Send Disable 19 1 RTSDISSelect 0 No effect 0x0 1 Drives the pin RTS to 1 0x1 RTSEN Request to Send Enable 18 1 RTSENSelect 0 No effect 0x0 1 Drives the pin RTS to 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 CTSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 ITER Max number of Repetitions Reached 10 1 ITERSelect 0 Maximum number of repetitions has not been reached since the last RSIT 0x0 1 Maximum number of repetitions has been reached since the last RSIT 0x1 LINBE LIN Bit Error 25 1 LINBLS LIN Bus Line Status 23 1 LINBLSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 LINCE LIN Checksum Error 28 1 LINHTE LIN Header Timeout Error 31 1 LINHTESelect 0 COMM_RX is at 0 0x0 1 COMM_RX is at 1 0x1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINIPE LIN Identifier Parity Error 27 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINSNRE LIN Slave Not Responding Error 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINSTESelect 0 COMM_TX is at 0 0x0 1 COMM_TX is at 1 0x1 LINTC LIN Transfer Conpleted 15 1 MANERR Manchester Error 24 1 MANERRSelect 0 No Manchester error has been detected since the last RSTSTA 0x0 1 At least one Manchester error has been detected since the last RSTSTA 0x1 NACK Non Acknowledge 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 UNRE SPI Underrun Error 10 1 UNRESelect 0 No SPI underrun error has occurred since the last RSTSTA 0x0 1 At least one SPI underrun error has occurred since the last RSTSTA 0x1 FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 FI_DI_RATIOSelect DISABLE Baud Rate = 0 0x0 IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 ITER Iteration Interrupt Disable 10 1 ITERSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINBE LIN Bus Error Interrupt Disable 25 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINHTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINSTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Disable 15 1 MANE Manchester Error Interrupt Disable 20 1 MANEA Manchester Error Interrupt Disable 24 1 MANEASelect 0 No effect 0x0 1 Disables the corresponding interrupt 0x1 NACK Non Acknowledge Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 UNRE SPI Underrun Error Interrupt Disable 10 1 UNRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 ITER Iteration Interrupt Enable 10 1 ITERSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINBE LIN Bus Error Interrupt Enable 25 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINHTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINSTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Enable 15 1 MANE Manchester Error Interrupt Enable 20 1 MANEA Manchester Error Interrupt Enable 24 1 MANEASelect 0 No effect 0x0 1 Enables the interrupt 0x1 NACK Non Acknowledge Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 UNRE SPI Underrun Error Interrupt Enable 10 1 UNRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 IFR IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER Irda filter 0 8 IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 ITER Iteration Interrupt Mask 10 1 ITERSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBE LIN Bus Error Interrupt Mask 25 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINHTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINID LIN Identifier Sent or LIN Received Interrupt Mask 14 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINSTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINTC LIN Transfer Conpleted Interrupt Mask 15 1 MANE Manchester Error Interrupt Mask 20 1 MANEA Manchester Error Interrupt Mask 24 1 MANEASelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 NACK Non Acknowledge Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 UNRE SPI Underrun Error Interrupt Mask 10 1 UNRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The LIN Controller transmits the response 0x0 SUBSCRIBE The LIN Controller receives the response 0x1 IGNORE The LIN Controller doesn't transmit and doesn't receive the response 0x2 PARDIS Parity Disable 2 1 PDCM PDC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift compensation 30 1 DRIFTSelect 0 The USART can not recover from an important clock drift 0x0 1 The USART can recover from clock drift. The 16X clock mode must be enabled 0x1 RX_MPOL Receiver Manchester Polarity 28 1 RX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 RX_PL Receiver Preamble Length 16 4 RX_PLSelect 0 The receiver preamble pattern detection is disabled 0x0 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 TX_PL Transmitter Preamble Length 0 4 TX_PLSelect 0 The Transmitter Preamble pattern generation is disabled 0x0 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal Mode 0x0 ECHO Automatic Echo. Receiver input is connected to the TXD pin 0x1 LOCAL_LOOP Local Loopback. Transmitter output is connected to the Receiver Input 0x2 REMOTE_LOOP Remote Loopback. RXD pin is internally connected to the TXD pin 0x3 CHRL Character Length. 6 2 CHRLSelect 5 5 bits 0x0 6 6 bits 0x1 7 7 bits 0x2 8 8 bits 0x3 CLKO Clock Output Select 18 1 CLKOSelect 0 The USART does not drive the SCK pin 0x0 1 The USART drives the SCK pin if USCLKS does not select the external clock SCK 0x1 CPHA SPI CLock Phase 8 1 CPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK 0x1 CPOL SPI Clock Polarity 16 1 CPOLSelect ZERO The inactive state value of SPCK is logic level zero 0x0 ONE The inactive state value of SPCK is logic level one 0x1 DSNACK Disable Successive NACK 21 1 DSNACKSelect 0 NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) 0x0 1 Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted 0x1 FILTER Infrared Receive Line Filter 28 1 FILTERSelect 0 The USART does not filter the receive line 0x0 1 The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) 0x1 INACK Inhibit Non Acknowledge 20 1 INACKSelect 0 The NACK is generated 0x0 1 The NACK is not generated 0x1 INVDATA Inverted data 23 1 MAN Manchester Encoder/Decoder Enable 29 1 MANSelect 0 Manchester Encoder/Decoder is disabled 0x0 1 Manchester Encoder/Decoder is enabled 0x1 MAX_ITERATION Max interation 24 3 MODE Usart Mode 0 4 MODESelect NORMAL Normal 0x0 RS485 RS485 0x1 HARDWARE Hardware Handshaking 0x2 MODEM Modem 0x3 ISO7816_T0 IS07816 Protocol: T = 0 0x4 ISO7816_T1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_Master LIN Master 0xa LIN_Slave LIN Slave 0xb SPI_Master SPI Master 0xe SPI_Slave SPI Slave 0xf MODE9 9-bit Character Length 17 1 MODE9Select 0 CHRL defines character length 0x0 1 9-bit character length 0x1 MODSYNC Manchester Synchronization Mode 30 1 MODSYNCSelect 0 The Manchester Start bit is a 0 to 1 transition 0x0 1 The Manchester Start bit is a 1 to 0 transition 0x1 MSBF Bit Order 16 1 MSBFSelect LSBF Least Significant Bit first 0x0 MSBF Most Significant Bit first 0x1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect 1 1 stop bit 0x0 1_5 1.5 stop bits (Only valid if SYNC=0) 0x1 2 2 stop bits 0x2 ONEBIT Start Frame Delimiter selector 31 1 ONEBITSelect 0 Start Frame delimiter is COMMAND or DATA SYNC 0x0 1 Start Frame delimiter is One Bit 0x1 OVER Oversampling Mode 19 1 OVERSelect X16 16x Oversampling 0x0 X8 8x Oversampling 0x1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NONE No Parity 0x4 5 No Parity 0x5 MULTI Multi-drop mode 0x6 7 Multi-drop mode 0x7 SYNC Synchronous Mode Select 8 1 SYNCSelect 0 USART operates in Synchronous Mode 0x0 1 USART operates in Asynchronous Mode 0x1 USCLKS Clock Selection 4 2 USCLKSSelect MCK MCK 0x0 MCK_DIV MCK / DIV 0x1 SCK SCK 0x3 VAR_SYNC Variable synchronization of command/data sync Start Frame Delimiter 22 1 VAR_SYNCSelect 0 User defined configuration of command or data sync field depending on SYNC value 0x0 1 The sync field is updated when a character is written into THR register 0x1 NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Error number during ISO7816 transfers 0 8 RHR Receiver Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 RXSYNHSelect 0 Last character received is a Data 0x0 1 Last character received is a Command 0x1 RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 TOSelect DISABLE Disables the RX Time-out function 0x0 THR Transmitter Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be transmitted 15 1 TXSYNHSelect 0 The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC 0x0 1 The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC 0x1 TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 TGSelect DISABLE Disables the TX Timeguard function. 0x0 USART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CDSelect DISABLE Disables the clock 0x0 BYPASS Clock Divisor Bypass 0x1 2 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD); Baud Rate (Synchronous Mode) = Selected Clock/CD; 0x2 FP Fractional Part 16 3 FPSelect 0 Fractional divider is disabled 0x0 USART_CR Control Register LIN_MODE 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 LINABT Abort the current LIN transmission 20 1 LINWKUP Sends a wakeup signal on the LIN bus 21 1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RTSDIS Request to Send Disable 19 1 RTSDISSelect 0 No effect 0x0 1 Drives the pin RTS to 1 0x1 RTSEN Request to Send Enable 18 1 RTSENSelect 0 No effect 0x0 1 Drives the pin RTS to 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 USART_CSR Channel Status Register LIN_MODE 0x14 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 ITER Max number of Repetitions Reached 10 1 ITERSelect 0 Maximum number of repetitions has not been reached since the last RSIT 0x0 1 Maximum number of repetitions has been reached since the last RSIT 0x1 LINBE LIN Bit Error 25 1 LINBLS LIN Bus Line Status 23 1 LINBLSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 LINCE LIN Checksum Error 28 1 LINHTE LIN Header Timeout Error 31 1 LINHTESelect 0 COMM_RX is at 0 0x0 1 COMM_RX is at 1 0x1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINIPE LIN Identifier Parity Error 27 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINSNRE LIN Slave Not Responding Error 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINSTESelect 0 COMM_TX is at 0 0x0 1 COMM_TX is at 1 0x1 LINTC LIN Transfer Conpleted 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 USART_FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 FI_DI_RATIOSelect DISABLE Baud Rate = 0 0x0 USART_IDR Interrupt Disable Register LIN_MODE 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 ITER Iteration Interrupt Disable 10 1 ITERSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINBE LIN Bus Error Interrupt Disable 25 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINHTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINSTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Disable 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 USART_IER Interrupt Enable Register LIN_MODE 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 ITER Iteration Interrupt Enable 10 1 ITERSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINBE LIN Bus Error Interrupt Enable 25 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINHTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINSTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Enable 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 USART_IFR IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER Irda filter 0 8 USART_IMR Interrupt Mask Register LIN_MODE 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 ITER Iteration Interrupt Mask 10 1 ITERSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBE LIN Bus Error Interrupt Mask 25 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINHTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINID LIN Identifier Sent or LIN Received Interrupt Mask 14 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINSTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINTC LIN Transfer Conpleted Interrupt Mask 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 USART_LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 USART_LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 USART_LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The LIN Controller transmits the response 0x0 SUBSCRIBE The LIN Controller receives the response 0x1 IGNORE The LIN Controller doesn't transmit and doesn't receive the response 0x2 PARDIS Parity Disable 2 1 PDCM PDC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 USART_MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift compensation 30 1 DRIFTSelect 0 The USART can not recover from an important clock drift 0x0 1 The USART can recover from clock drift. The 16X clock mode must be enabled 0x1 RX_MPOL Receiver Manchester Polarity 28 1 RX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 RX_PL Receiver Preamble Length 16 4 RX_PLSelect 0 The receiver preamble pattern detection is disabled 0x0 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 TX_PL Transmitter Preamble Length 0 4 TX_PLSelect 0 The Transmitter Preamble pattern generation is disabled 0x0 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 USART_MR Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal Mode 0x0 ECHO Automatic Echo. Receiver input is connected to the TXD pin 0x1 LOCAL_LOOP Local Loopback. Transmitter output is connected to the Receiver Input 0x2 REMOTE_LOOP Remote Loopback. RXD pin is internally connected to the TXD pin 0x3 CHRL Character Length. 6 2 CHRLSelect 5 5 bits 0x0 6 6 bits 0x1 7 7 bits 0x2 8 8 bits 0x3 CLKO Clock Output Select 18 1 CLKOSelect 0 The USART does not drive the SCK pin 0x0 1 The USART drives the SCK pin if USCLKS does not select the external clock SCK 0x1 CPHA SPI CLock Phase 8 1 CPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK 0x1 CPOL SPI Clock Polarity 16 1 CPOLSelect ZERO The inactive state value of SPCK is logic level zero 0x0 ONE The inactive state value of SPCK is logic level one 0x1 DSNACK Disable Successive NACK 21 1 DSNACKSelect 0 NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) 0x0 1 Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted 0x1 FILTER Infrared Receive Line Filter 28 1 FILTERSelect 0 The USART does not filter the receive line 0x0 1 The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) 0x1 INACK Inhibit Non Acknowledge 20 1 INACKSelect 0 The NACK is generated 0x0 1 The NACK is not generated 0x1 INVDATA Inverted data 23 1 MAX_ITERATION Max interation 24 3 MODE Usart Mode 0 4 MODESelect NORMAL Normal 0x0 RS485 RS485 0x1 HARDWARE Hardware Handshaking 0x2 MODEM Modem 0x3 ISO7816_T0 IS07816 Protocol: T = 0 0x4 ISO7816_T1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_Master LIN Master 0xa LIN_Slave LIN Slave 0xb SPI_Master SPI Master 0xe SPI_Slave SPI Slave 0xf MODE9 9-bit Character Length 17 1 MODE9Select 0 CHRL defines character length 0x0 1 9-bit character length 0x1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect 1 1 stop bit 0x0 1_5 1.5 stop bits (Only valid if SYNC=0) 0x1 2 2 stop bits 0x2 OVER Oversampling Mode 19 1 OVERSelect X16 16x Oversampling 0x0 X8 8x Oversampling 0x1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NONE No Parity 0x4 5 No Parity 0x5 MULTI Multi-drop mode 0x6 7 Multi-drop mode 0x7 USCLKS Clock Selection 4 2 USCLKSSelect MCK MCK 0x0 MCK_DIV MCK / DIV 0x1 SCK SCK 0x3 USART_NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Error number during ISO7816 transfers 0 8 USART_RHR Receiver Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 RXSYNHSelect 0 Last character received is a Data 0x0 1 Last character received is a Command 0x1 USART_RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 TOSelect DISABLE Disables the RX Time-out function 0x0 USART_THR Transmitter Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be transmitted 15 1 TXSYNHSelect 0 The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC 0x0 1 The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC 0x1 USART_TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 TGSelect DISABLE Disables the TX Timeguard function. 0x0 USART_VERSION Version Register 0xFC 32 read-only n 0x0 0x0 MFN MFN 16 4 VERSION Version 0 12 USART_WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPENSelect 0 Disables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) 0x0 1 Enables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) 0x1 WPKEY Write Protect Key 8 24 USART_WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPV Write Protect Violation Status 0 1 WPVSelect 0 No Write Protect Violation has occurred since the last read of the WPSR register 0x0 1 A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC 0x1 WPVSRC Write Protect Violation Source 8 16 VERSION Version Register 0xFC 32 read-only n 0x0 0x0 MFN MFN 16 4 VERSION Version 0 12 WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPENSelect 0 Disables the Write Protect if WPKEY corresponds to 0x858365 ( USA in ACII) 0x0 1 Enables the Write Protect if WPKEY corresponds to 0x858365 ( USA in ACII) 0x1 WPKEY Write Protect Key 8 24 WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPV Write Protect Violation Status 0 1 WPVSelect 0 No Write Protect Violation has occurred since the last read of the WPSR register 0x0 1 A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC 0x1 WPVSRC Write Protect Violation Source 8 16 USART3 Universal Synchronous Asynchronous Receiver Transmitter 3 USART 0x0 0x0 0x400 registers n USART3 68 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CDSelect DISABLE Disables the clock 0x0 BYPASS Clock Divisor Bypass 0x1 2 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD) Baud Rate (Synchronous Mode) = Selected Clock/CD 0x2 FP Fractional Part 16 3 FPSelect 0 Fractional divider is disabled 0x0 CR Control Register 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 FCS Force SPI Chip Select 18 1 FCSSelect 0 No effect 0x0 1 Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer) 0x1 LINABT Abort the current LIN transmission 20 1 LINWKUP Sends a wakeup signal on the LIN bus 21 1 RCS Release SPI Chip Select 19 1 RCSSelect 0 No effect 0x0 1 Releases the Slave Select Line NSS (RTS pin) 0x1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RTSDIS Request to Send Disable 19 1 RTSDISSelect 0 No effect 0x0 1 Drives the pin RTS to 1 0x1 RTSEN Request to Send Enable 18 1 RTSENSelect 0 No effect 0x0 1 Drives the pin RTS to 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 CTSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 ITER Max number of Repetitions Reached 10 1 ITERSelect 0 Maximum number of repetitions has not been reached since the last RSIT 0x0 1 Maximum number of repetitions has been reached since the last RSIT 0x1 LINBE LIN Bit Error 25 1 LINBLS LIN Bus Line Status 23 1 LINBLSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 LINCE LIN Checksum Error 28 1 LINHTE LIN Header Timeout Error 31 1 LINHTESelect 0 COMM_RX is at 0 0x0 1 COMM_RX is at 1 0x1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINIPE LIN Identifier Parity Error 27 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINSNRE LIN Slave Not Responding Error 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINSTESelect 0 COMM_TX is at 0 0x0 1 COMM_TX is at 1 0x1 LINTC LIN Transfer Conpleted 15 1 MANERR Manchester Error 24 1 MANERRSelect 0 No Manchester error has been detected since the last RSTSTA 0x0 1 At least one Manchester error has been detected since the last RSTSTA 0x1 NACK Non Acknowledge 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 UNRE SPI Underrun Error 10 1 UNRESelect 0 No SPI underrun error has occurred since the last RSTSTA 0x0 1 At least one SPI underrun error has occurred since the last RSTSTA 0x1 FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 FI_DI_RATIOSelect DISABLE Baud Rate = 0 0x0 IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 ITER Iteration Interrupt Disable 10 1 ITERSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINBE LIN Bus Error Interrupt Disable 25 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINHTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINSTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Disable 15 1 MANE Manchester Error Interrupt Disable 20 1 MANEA Manchester Error Interrupt Disable 24 1 MANEASelect 0 No effect 0x0 1 Disables the corresponding interrupt 0x1 NACK Non Acknowledge Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 UNRE SPI Underrun Error Interrupt Disable 10 1 UNRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 ITER Iteration Interrupt Enable 10 1 ITERSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINBE LIN Bus Error Interrupt Enable 25 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINHTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINSTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Enable 15 1 MANE Manchester Error Interrupt Enable 20 1 MANEA Manchester Error Interrupt Enable 24 1 MANEASelect 0 No effect 0x0 1 Enables the interrupt 0x1 NACK Non Acknowledge Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 UNRE SPI Underrun Error Interrupt Enable 10 1 UNRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 IFR IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER Irda filter 0 8 IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 ITER Iteration Interrupt Mask 10 1 ITERSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBE LIN Bus Error Interrupt Mask 25 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINHTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINID LIN Identifier Sent or LIN Received Interrupt Mask 14 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINSTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINTC LIN Transfer Conpleted Interrupt Mask 15 1 MANE Manchester Error Interrupt Mask 20 1 MANEA Manchester Error Interrupt Mask 24 1 MANEASelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 NACK Non Acknowledge Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 UNRE SPI Underrun Error Interrupt Mask 10 1 UNRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The LIN Controller transmits the response 0x0 SUBSCRIBE The LIN Controller receives the response 0x1 IGNORE The LIN Controller doesn't transmit and doesn't receive the response 0x2 PARDIS Parity Disable 2 1 PDCM PDC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift compensation 30 1 DRIFTSelect 0 The USART can not recover from an important clock drift 0x0 1 The USART can recover from clock drift. The 16X clock mode must be enabled 0x1 RX_MPOL Receiver Manchester Polarity 28 1 RX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 RX_PL Receiver Preamble Length 16 4 RX_PLSelect 0 The receiver preamble pattern detection is disabled 0x0 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 TX_PL Transmitter Preamble Length 0 4 TX_PLSelect 0 The Transmitter Preamble pattern generation is disabled 0x0 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal Mode 0x0 ECHO Automatic Echo. Receiver input is connected to the TXD pin 0x1 LOCAL_LOOP Local Loopback. Transmitter output is connected to the Receiver Input 0x2 REMOTE_LOOP Remote Loopback. RXD pin is internally connected to the TXD pin 0x3 CHRL Character Length. 6 2 CHRLSelect 5 5 bits 0x0 6 6 bits 0x1 7 7 bits 0x2 8 8 bits 0x3 CLKO Clock Output Select 18 1 CLKOSelect 0 The USART does not drive the SCK pin 0x0 1 The USART drives the SCK pin if USCLKS does not select the external clock SCK 0x1 CPHA SPI CLock Phase 8 1 CPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK 0x1 CPOL SPI Clock Polarity 16 1 CPOLSelect ZERO The inactive state value of SPCK is logic level zero 0x0 ONE The inactive state value of SPCK is logic level one 0x1 DSNACK Disable Successive NACK 21 1 DSNACKSelect 0 NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) 0x0 1 Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted 0x1 FILTER Infrared Receive Line Filter 28 1 FILTERSelect 0 The USART does not filter the receive line 0x0 1 The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) 0x1 INACK Inhibit Non Acknowledge 20 1 INACKSelect 0 The NACK is generated 0x0 1 The NACK is not generated 0x1 INVDATA Inverted data 23 1 MAN Manchester Encoder/Decoder Enable 29 1 MANSelect 0 Manchester Encoder/Decoder is disabled 0x0 1 Manchester Encoder/Decoder is enabled 0x1 MAX_ITERATION Max interation 24 3 MODE Usart Mode 0 4 MODESelect NORMAL Normal 0x0 RS485 RS485 0x1 HARDWARE Hardware Handshaking 0x2 MODEM Modem 0x3 ISO7816_T0 IS07816 Protocol: T = 0 0x4 ISO7816_T1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_Master LIN Master 0xa LIN_Slave LIN Slave 0xb SPI_Master SPI Master 0xe SPI_Slave SPI Slave 0xf MODE9 9-bit Character Length 17 1 MODE9Select 0 CHRL defines character length 0x0 1 9-bit character length 0x1 MODSYNC Manchester Synchronization Mode 30 1 MODSYNCSelect 0 The Manchester Start bit is a 0 to 1 transition 0x0 1 The Manchester Start bit is a 1 to 0 transition 0x1 MSBF Bit Order 16 1 MSBFSelect LSBF Least Significant Bit first 0x0 MSBF Most Significant Bit first 0x1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect 1 1 stop bit 0x0 1_5 1.5 stop bits (Only valid if SYNC=0) 0x1 2 2 stop bits 0x2 ONEBIT Start Frame Delimiter selector 31 1 ONEBITSelect 0 Start Frame delimiter is COMMAND or DATA SYNC 0x0 1 Start Frame delimiter is One Bit 0x1 OVER Oversampling Mode 19 1 OVERSelect X16 16x Oversampling 0x0 X8 8x Oversampling 0x1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NONE No Parity 0x4 5 No Parity 0x5 MULTI Multi-drop mode 0x6 7 Multi-drop mode 0x7 SYNC Synchronous Mode Select 8 1 SYNCSelect 0 USART operates in Synchronous Mode 0x0 1 USART operates in Asynchronous Mode 0x1 USCLKS Clock Selection 4 2 USCLKSSelect MCK MCK 0x0 MCK_DIV MCK / DIV 0x1 SCK SCK 0x3 VAR_SYNC Variable synchronization of command/data sync Start Frame Delimiter 22 1 VAR_SYNCSelect 0 User defined configuration of command or data sync field depending on SYNC value 0x0 1 The sync field is updated when a character is written into THR register 0x1 NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Error number during ISO7816 transfers 0 8 RHR Receiver Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 RXSYNHSelect 0 Last character received is a Data 0x0 1 Last character received is a Command 0x1 RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 TOSelect DISABLE Disables the RX Time-out function 0x0 THR Transmitter Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be transmitted 15 1 TXSYNHSelect 0 The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC 0x0 1 The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC 0x1 TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 TGSelect DISABLE Disables the TX Timeguard function. 0x0 USART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CDSelect DISABLE Disables the clock 0x0 BYPASS Clock Divisor Bypass 0x1 2 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD); Baud Rate (Synchronous Mode) = Selected Clock/CD; 0x2 FP Fractional Part 16 3 FPSelect 0 Fractional divider is disabled 0x0 USART_CR Control Register LIN_MODE 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTRDISSelect 0 No effect 0x0 1 Drives the pin DTR to 1 0x1 DTREN Data Terminal Ready Enable 16 1 DTRENSelect 0 No effect 0x0 1 Drives the pin DTR at 0 0x1 LINABT Abort the current LIN transmission 20 1 LINWKUP Sends a wakeup signal on the LIN bus 21 1 RETTO Rearm Time-out 15 1 RETTOSelect 0 No effect 0x0 1 Restart Time-out 0x1 RSTIT Reset Iterations 13 1 RSTITSelect 0 No effect 0x0 1 Resets ITERATION in CSR. No effect if the ISO7816 is not enabled 0x1 RSTNACK Reset Non Acknowledge 14 1 RSTNACKSelect 0 No effect 0x0 1 Resets NACK in CSR 0x1 RSTRX Reset Receiver 2 1 RSTRXSelect 0 No effect 0x0 1 Resets the receiver 0x1 RSTSTA Reset Status Bits 8 1 RSTSTASelect 0 No effect 0x0 1 Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR 0x1 RSTTX Reset Transmitter 3 1 RSTTXSelect 0 No effect 0x0 1 Resets the transmitter 0x1 RTSDIS Request to Send Disable 19 1 RTSDISSelect 0 No effect 0x0 1 Drives the pin RTS to 1 0x1 RTSEN Request to Send Enable 18 1 RTSENSelect 0 No effect 0x0 1 Drives the pin RTS to 0 0x1 RXDIS Receiver Disable 5 1 RXDISSelect 0 No effect 0x0 1 Disables the receiver 0x1 RXEN Receiver Enable 4 1 RXENSelect 0 No effect 0x0 1 Enables the receiver, if RXDIS is 0 0x1 SENDA Send Address 12 1 SENDASelect 0 No effect 0x0 1 In Multi-drop Mode only, the next character written to the THR is sent with the address bit set 0x1 STPBRK Stop Break 10 1 STPBRKSelect 0 No effect 0x0 1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted 0x1 STTBRK Start Break 9 1 STTBRKSelect 0 No effect 0x0 1 Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted 0x1 STTTO Start Time-out 11 1 STTTOSelect 0 No effect 0x0 1 Starts waiting for a character before clocking the time-out counter 0x1 TXDIS Transmitter Disable 7 1 TXDISSelect 0 No effect 0x0 1 Disables the transmitter 0x1 TXEN Transmitter Enable 6 1 TXENSelect 0 No effect 0x0 1 Enables the transmitter if TXDIS is 0 0x1 USART_CSR Channel Status Register LIN_MODE 0x14 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Flag 19 1 CTSICSelect 0 No input change has been detected on the CTS pin since the last read of CSR 0x0 1 At least one input change has been detected on the CTS pin since the last read of CSR 0x1 DCD Image of DCD Input 22 1 DCDSelect 0 DCD is at 0 0x0 1 DCD is at 1 0x1 DCDIC Data Carrier Detect Input Change Flag 18 1 DCDICSelect 0 No input change has been detected on the DCD pin since the last read of CSR 0x0 1 At least one input change has been detected on the DCD pin since the last read of CSR 0x1 DSR Image of DSR Input 21 1 DSRSelect 0 DSR is at 0 0x0 1 DSR is at 1 0x1 DSRIC Data Set Ready Input Change Flag 17 1 DSRICSelect 0 No input change has been detected on the DSR pin since the last read of CSR 0x0 1 At least one input change has been detected on the DSR pin since the last read of CSR 0x1 FRAME Framing Error 6 1 FRAMESelect 0 No stop bit has been detected low since the last RSTSTA 0x0 1 At least one stop bit has been detected low since the last RSTSTA 0x1 ITER Max number of Repetitions Reached 10 1 ITERSelect 0 Maximum number of repetitions has not been reached since the last RSIT 0x0 1 Maximum number of repetitions has been reached since the last RSIT 0x1 LINBE LIN Bit Error 25 1 LINBLS LIN Bus Line Status 23 1 LINBLSSelect 0 CTS is at 0 0x0 1 CTS is at 1 0x1 LINCE LIN Checksum Error 28 1 LINHTE LIN Header Timeout Error 31 1 LINHTESelect 0 COMM_RX is at 0 0x0 1 COMM_RX is at 1 0x1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINIPE LIN Identifier Parity Error 27 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINSNRE LIN Slave Not Responding Error 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINSTESelect 0 COMM_TX is at 0 0x0 1 COMM_TX is at 1 0x1 LINTC LIN Transfer Conpleted 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received 13 1 NACKSelect 0 No Non Acknowledge has not been detected since the last RSTNACK 0x0 1 At least one Non Acknowledge has been detected since the last RSTNACK 0x1 OVRE Overrun Error 5 1 OVRESelect 0 No overrun error has occurred since since the last RSTSTA 0x0 1 At least one overrun error has occurred since the last RSTSTA 0x1 PARE Parity Error 7 1 PARESelect 0 No parity error has been detected since the last RSTSTA 0x0 1 At least one parity error has been detected since the last RSTSTA 0x1 RI Image of RI Input 20 1 RISelect 0 RI is at 0 0x0 1 RI is at 1 0x1 RIIC Ring Indicator Input Change Flag 16 1 RIICSelect 0 No input change has been detected on the RI pin since the last read of CSR 0x0 1 At least one input change has been detected on the RI pin since the last read of CSR 0x1 RXBRK Break Received/End of Break 2 1 RXBRKSelect 0 No Break received or End of Break detected since the last RSTSTA 0x0 1 Break Received or End of Break detected since the last RSTSTA 0x1 RXBUFF Reception Buffer Full 12 1 RXBUFFSelect 0 The signal Buffer Full from the Receive PDC channel is inactive 0x0 1 The signal Buffer Full from the Receive PDC channel is active 0x1 RXRDY Receiver Ready 0 1 RXRDYSelect 0 No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled 0x0 1 At least one complete character has been received and RHR has not yet been read 0x1 TIMEOUT Receiver Time-out 8 1 TIMEOUTSelect 0 There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 0x0 1 There has been a time-out since the last Start Time-out command 0x1 TXBUFE Transmission Buffer Empty 11 1 TXBUFESelect 0 The signal Buffer Empty from the Transmit PDC channel is inactive 0x0 1 The signal Buffer Empty from the Transmit PDC channel is active 0x1 TXEMPTY Transmitter Empty 9 1 TXEMPTYSelect 0 There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled 0x0 1 There is at least one character in either THR or the Transmit Shift Register 0x1 TXRDY Transmitter Ready 1 1 TXRDYSelect 0 A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 0x0 1 There is no character in the THR 0x1 USART_FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 FI_DI_RATIOSelect DISABLE Baud Rate = 0 0x0 USART_IDR Interrupt Disable Register LIN_MODE 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 CTSICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DCDICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 DSRIC Data Set Ready Input Change Disable 17 1 DSRICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 FRAME Framing Error Interrupt Disable 6 1 FRAMESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 ITER Iteration Interrupt Disable 10 1 ITERSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINBE LIN Bus Error Interrupt Disable 25 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINHTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINSTESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Disable 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Disable 13 1 NACKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 OVRE Overrun Error Interrupt Disable 5 1 OVRESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 PARE Parity Error Interrupt Disable 7 1 PARESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RIIC Ring Indicator Input Change Disable 16 1 RIICSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBRK Receiver Break Interrupt Disable 2 1 RXBRKSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXBUFF Buffer Full Interrupt Disable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 RXRDY Receiver Ready Interrupt Disable 0 1 RXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TIMEOUT Time-out Interrupt Disable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Disable 11 1 TXBUFESelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Disable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Disable 1 1 TXRDYSelect 0 No Effect 0x0 1 Disables the interrupt 0x1 USART_IER Interrupt Enable Register LIN_MODE 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 CTSICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DCDICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 DSRIC Data Set Ready Input Change Enable 17 1 DSRICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 FRAME Framing Error Interrupt Enable 6 1 FRAMESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 ITER Iteration Interrupt Enable 10 1 ITERSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINBE LIN Bus Error Interrupt Enable 25 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINHTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINSTESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 LINTC LIN Transfer Conpleted Interrupt Enable 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Enable 13 1 NACKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 OVRE Overrun Error Interrupt Enable 5 1 OVRESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 PARE Parity Error Interrupt Enable 7 1 PARESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RIIC Ring Indicator Input Change Enable 16 1 RIICSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBRK Receiver Break Interrupt Enable 2 1 RXBRKSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXBUFF Buffer Full Interrupt Enable 12 1 RXBUFFSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 RXRDY Receiver Ready Interrupt Enable 0 1 RXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TIMEOUT Time-out Interrupt Enable 8 1 TIMEOUTSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXBUFE Buffer Empty Interrupt Enable 11 1 TXBUFESelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXEMPTY Transmitter Empty Interrupt Enable 9 1 TXEMPTYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 TXRDY Transmitter Ready Interrupt Enable 1 1 TXRDYSelect 0 No Effect 0x0 1 Enables the interrupt 0x1 USART_IFR IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER Irda filter 0 8 USART_IMR Interrupt Mask Register LIN_MODE 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 CTSICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DCDICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 DSRIC Data Set Ready Input Change Mask 17 1 DSRICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 FRAME Framing Error Interrupt Mask 6 1 FRAMESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 ITER Iteration Interrupt Mask 10 1 ITERSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINBE LIN Bus Error Interrupt Mask 25 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINHTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINID LIN Identifier Sent or LIN Received Interrupt Mask 14 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINSTESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 LINTC LIN Transfer Conpleted Interrupt Mask 15 1 NACK Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask 13 1 NACKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 OVRE Overrun Error Interrupt Mask 5 1 OVRESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 PARE Parity Error Interrupt Mask 7 1 PARESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RIIC Ring Indicator Input Change Mask 16 1 RIICSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBRK Receiver Break Interrupt Mask 2 1 RXBRKSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXBUFF Buffer Full Interrupt Mask 12 1 RXBUFFSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 RXRDY RXRDY Interrupt Mask 0 1 RXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TIMEOUT Time-out Interrupt Mask 8 1 TIMEOUTSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXBUFE Buffer Empty Interrupt Mask 11 1 TXBUFESelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXEMPTYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 TXRDY TXRDY Interrupt Mask 1 1 TXRDYSelect 0 The interrupt is disabled 0x0 1 The interrupt is enabled 0x1 USART_LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 USART_LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 USART_LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The LIN Controller transmits the response 0x0 SUBSCRIBE The LIN Controller receives the response 0x1 IGNORE The LIN Controller doesn't transmit and doesn't receive the response 0x2 PARDIS Parity Disable 2 1 PDCM PDC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 USART_MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift compensation 30 1 DRIFTSelect 0 The USART can not recover from an important clock drift 0x0 1 The USART can recover from clock drift. The 16X clock mode must be enabled 0x1 RX_MPOL Receiver Manchester Polarity 28 1 RX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 RX_PL Receiver Preamble Length 16 4 RX_PLSelect 0 The receiver preamble pattern detection is disabled 0x0 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_MPOLSelect 0 Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition 0x0 1 Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition 0x1 TX_PL Transmitter Preamble Length 0 4 TX_PLSelect 0 The Transmitter Preamble pattern generation is disabled 0x0 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect 0 ALL_ONE 0x0 1 ALL_ZERO 0x1 2 ZERO_ONE 0x2 3 ONE_ZERO 0x3 USART_MR Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal Mode 0x0 ECHO Automatic Echo. Receiver input is connected to the TXD pin 0x1 LOCAL_LOOP Local Loopback. Transmitter output is connected to the Receiver Input 0x2 REMOTE_LOOP Remote Loopback. RXD pin is internally connected to the TXD pin 0x3 CHRL Character Length. 6 2 CHRLSelect 5 5 bits 0x0 6 6 bits 0x1 7 7 bits 0x2 8 8 bits 0x3 CLKO Clock Output Select 18 1 CLKOSelect 0 The USART does not drive the SCK pin 0x0 1 The USART drives the SCK pin if USCLKS does not select the external clock SCK 0x1 CPHA SPI CLock Phase 8 1 CPHASelect 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK 0x0 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK 0x1 CPOL SPI Clock Polarity 16 1 CPOLSelect ZERO The inactive state value of SPCK is logic level zero 0x0 ONE The inactive state value of SPCK is logic level one 0x1 DSNACK Disable Successive NACK 21 1 DSNACKSelect 0 NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) 0x0 1 Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted 0x1 FILTER Infrared Receive Line Filter 28 1 FILTERSelect 0 The USART does not filter the receive line 0x0 1 The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) 0x1 INACK Inhibit Non Acknowledge 20 1 INACKSelect 0 The NACK is generated 0x0 1 The NACK is not generated 0x1 INVDATA Inverted data 23 1 MAX_ITERATION Max interation 24 3 MODE Usart Mode 0 4 MODESelect NORMAL Normal 0x0 RS485 RS485 0x1 HARDWARE Hardware Handshaking 0x2 MODEM Modem 0x3 ISO7816_T0 IS07816 Protocol: T = 0 0x4 ISO7816_T1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_Master LIN Master 0xa LIN_Slave LIN Slave 0xb SPI_Master SPI Master 0xe SPI_Slave SPI Slave 0xf MODE9 9-bit Character Length 17 1 MODE9Select 0 CHRL defines character length 0x0 1 9-bit character length 0x1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect 1 1 stop bit 0x0 1_5 1.5 stop bits (Only valid if SYNC=0) 0x1 2 2 stop bits 0x2 OVER Oversampling Mode 19 1 OVERSelect X16 16x Oversampling 0x0 X8 8x Oversampling 0x1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NONE No Parity 0x4 5 No Parity 0x5 MULTI Multi-drop mode 0x6 7 Multi-drop mode 0x7 USCLKS Clock Selection 4 2 USCLKSSelect MCK MCK 0x0 MCK_DIV MCK / DIV 0x1 SCK SCK 0x3 USART_NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Error number during ISO7816 transfers 0 8 USART_RHR Receiver Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 RXSYNHSelect 0 Last character received is a Data 0x0 1 Last character received is a Command 0x1 USART_RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 TOSelect DISABLE Disables the RX Time-out function 0x0 USART_THR Transmitter Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be transmitted 15 1 TXSYNHSelect 0 The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC 0x0 1 The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC 0x1 USART_TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 TGSelect DISABLE Disables the TX Timeguard function. 0x0 USART_VERSION Version Register 0xFC 32 read-only n 0x0 0x0 MFN MFN 16 4 VERSION Version 0 12 USART_WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPENSelect 0 Disables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) 0x0 1 Enables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) 0x1 WPKEY Write Protect Key 8 24 USART_WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPV Write Protect Violation Status 0 1 WPVSelect 0 No Write Protect Violation has occurred since the last read of the WPSR register 0x0 1 A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC 0x1 WPVSRC Write Protect Violation Source 8 16 VERSION Version Register 0xFC 32 read-only n 0x0 0x0 MFN MFN 16 4 VERSION Version 0 12 WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPENSelect 0 Disables the Write Protect if WPKEY corresponds to 0x858365 ( USA in ACII) 0x0 1 Enables the Write Protect if WPKEY corresponds to 0x858365 ( USA in ACII) 0x1 WPKEY Write Protect Key 8 24 WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPV Write Protect Violation Status 0 1 WPVSelect 0 No Write Protect Violation has occurred since the last read of the WPSR register 0x0 1 A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC 0x1 WPVSRC Write Protect Violation Source 8 16 USBC USB 2.0 Interface USBC 0x0 0x0 0x1000 registers n USBC 18 UADDRSIZE IP PB address size Register 0x820 32 read-only n 0x0 0x0 UADDRSIZE IP PB Address Size 0 32 UDCON Device General Control Register 0x0 32 read-write n 0x0 0x0 ADDEN Address Enable 7 1 DETACH Detach 8 1 GNAK Global NAK 17 1 LS Low Speed Mode Force 12 1 OPMODE2 Specific Operational mode 16 1 RMWKUP Remote Wake-Up 9 1 SPDCONF Speed configuration 10 2 TSTJ Test mode J 13 1 TSTK Test mode K 14 1 TSTPCKT Test Packet mode 15 1 UADD USB Address 0 7 UDESC Endpoint descriptor table 0x830 32 read-write n 0x0 0x0 UDESCA USB Descriptor Address 0 32 UDFNUM Device Frame Number Register 0x20 32 read-only n 0x0 0x0 FNCERR Frame Number CRC Error 15 1 read-only FNUM Frame Number 3 11 read-only MFNUM Micro Frame Number 0 3 read-only UDINT Device Global Interupt Register 0x4 32 read-only n 0x0 0x0 EORSM End Of Resume Interrupt 5 1 read-only EORST End of Reset Interrupt 3 1 read-only EP0INT Endpoint 0 Interrupt 12 1 read-only EP1INT Endpoint 1 Interrupt 13 1 read-only EP2INT Endpoint 2 Interrupt 14 1 read-only EP3INT Endpoint 3 Interrupt 15 1 read-only EP4INT Endpoint 4 Interrupt 16 1 read-only EP5INT Endpoint 5 Interrupt 17 1 read-only EP6INT Endpoint 6 Interrupt 18 1 read-only EP7INT Endpoint 7 Interrupt 19 1 read-only MSOF Micro Start of Frame Interrupt 1 1 read-only SOF Start of Frame Interrupt 2 1 read-only SUSP Suspend Interrupt 0 1 read-only UPRSM Upstream Resume Interrupt 6 1 read-only WAKEUP Wake-Up Interrupt 4 1 read-only UDINTCLR Device Global Interrupt Clear Register 0x8 32 write-only n 0x0 0x0 EORSMC EORSM Interrupt Clear 5 1 write-only EORSTC EORST Interrupt Clear 3 1 write-only MSOFC MSOF Interrupt Clear 1 1 write-only SOFC SOF Interrupt Clear 2 1 write-only SUSPC SUSP Interrupt Clear 0 1 write-only UPRSMC UPRSM Interrupt Clear 6 1 write-only WAKEUPC WAKEUP Interrupt Clear 4 1 write-only UDINTE Device Global Interrupt Enable Register 0x10 32 read-only n 0x0 0x0 EORSME EORSM Interrupt Enable 5 1 read-only EORSTE EORST Interrupt Enable 3 1 read-only EP0INTE EP0INT Interrupt Enable 12 1 read-only EP1INTE EP1INT Interrupt Enable 13 1 read-only EP2INTE EP2INT Interrupt Enable 14 1 read-only EP3INTE EP3INT Interrupt Enable 15 1 read-only EP4INTE EP4INT Interrupt Enable 16 1 read-only EP5INTE EP5INT Interrupt Enable 17 1 read-only EP6INTE EP6INT Interrupt Enable 18 1 read-only EP7INTE EP7INT Interrupt Enable 19 1 read-only MSOFE MSOF Interrupt Enable 1 1 read-only SOFE SOF Interrupt Enable 2 1 read-only SUSPE SUSP Interrupt Enable 0 1 read-only UPRSME UPRSM Interrupt Enable 6 1 read-only WAKEUPE WAKEUP Interrupt Enable 4 1 read-only UDINTECLR Device Global Interrupt Enable Clear Register 0x14 32 write-only n 0x0 0x0 EORSMEC EORSM Interrupt Enable Clear 5 1 write-only EORSTEC EORST Interrupt Enable Clear 3 1 write-only EP0INTEC EP0INT Interrupt Enable Clear 12 1 write-only EP1INTEC EP1INT Interrupt Enable Clear 13 1 write-only EP2INTEC EP2INT Interrupt Enable Clear 14 1 write-only EP3INTEC EP3INT Interrupt Enable Clear 15 1 write-only EP4INTEC EP4INT Interrupt Enable Clear 16 1 write-only EP5INTEC EP5INT Interrupt Enable Clear 17 1 write-only EP6INTEC EP6INT Interrupt Enable Clear 18 1 write-only EP7INTEC EP7INT Interrupt Enable Clear 19 1 write-only MSOFEC MSOF Interrupt Enable Clear 1 1 write-only SOFEC SOF Interrupt Enable Clear 2 1 write-only SUSPEC SUSP Interrupt Enable Clear 0 1 write-only UPRSMEC UPRSM Interrupt Enable Clear 6 1 write-only WAKEUPEC WAKEUP Interrupt Enable Clear 4 1 write-only UDINTESET Device Global Interrupt Enable Set Register 0x18 32 write-only n 0x0 0x0 EORSMES EORSM Interrupt Enable Set 5 1 write-only EORSTES EORST Interrupt Enable Set 3 1 write-only EP0INTES EP0INT Interrupt Enable Set 12 1 write-only EP1INTES EP1INT Interrupt Enable Set 13 1 write-only EP2INTES EP2INT Interrupt Enable Set 14 1 write-only EP3INTES EP3INT Interrupt Enable Set 15 1 write-only EP4INTES EP4INT Interrupt Enable Set 16 1 write-only EP5INTES EP5INT Interrupt Enable Set 17 1 write-only EP6INTES EP6INT Interrupt Enable Set 18 1 write-only EP7INTES EP7INT Interrupt Enable Set 19 1 write-only MSOFES MSOF Interrupt Enable Set 1 1 write-only SOFES SOF Interrupt Enable Set 2 1 write-only SUSPES SUSP Interrupt Enable Set 0 1 write-only UPRSMES UPRSM Interrupt Enable Set 6 1 write-only WAKEUPES WAKEUP Interrupt Enable Set 4 1 write-only UDINTSET Device Global Interrupt Set Regsiter 0xC 32 write-only n 0x0 0x0 EORSMS EORSM Interrupt Set 5 1 write-only EORSTS EORST Interrupt Set 3 1 write-only MSOFS MSOF Interrupt Set 1 1 write-only SOFS SOF Interrupt Set 2 1 write-only SUSPS SUSP Interrupt Set 0 1 write-only UPRSMS UPRSM Interrupt Set 6 1 write-only WAKEUPS WAKEUP Interrupt Set 4 1 write-only UECFG0 Endpoint Configuration Register 0x100 32 read-write n 0x0 0x0 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE None 0x0 DOUBLE None 0x1 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT None 0x0 IN None 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 REPNB Redirected Endpoint Number 16 4 UECFG1 Endpoint Configuration Register 0x104 32 read-write n 0x0 0x0 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE None 0x0 DOUBLE None 0x1 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT None 0x0 IN None 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 REPNB Redirected Endpoint Number 16 4 UECFG2 Endpoint Configuration Register 0x108 32 read-write n 0x0 0x0 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE None 0x0 DOUBLE None 0x1 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT None 0x0 IN None 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 REPNB Redirected Endpoint Number 16 4 UECFG3 Endpoint Configuration Register 0x10C 32 read-write n 0x0 0x0 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE None 0x0 DOUBLE None 0x1 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT None 0x0 IN None 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 REPNB Redirected Endpoint Number 16 4 UECFG4 Endpoint Configuration Register 0x110 32 read-write n 0x0 0x0 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE None 0x0 DOUBLE None 0x1 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT None 0x0 IN None 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 REPNB Redirected Endpoint Number 16 4 UECFG5 Endpoint Configuration Register 0x114 32 read-write n 0x0 0x0 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE None 0x0 DOUBLE None 0x1 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT None 0x0 IN None 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 REPNB Redirected Endpoint Number 16 4 UECFG6 Endpoint Configuration Register 0x118 32 read-write n 0x0 0x0 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE None 0x0 DOUBLE None 0x1 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT None 0x0 IN None 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 REPNB Redirected Endpoint Number 16 4 UECFG7 Endpoint Configuration Register 0x11C 32 read-write n 0x0 0x0 EPBK Endpoint Bank 2 1 EPBKSelect SINGLE None 0x0 DOUBLE None 0x1 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT None 0x0 IN None 0x1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 REPNB Redirected Endpoint Number 16 4 UECON0 Endpoint Control Register 0x1C0 32 read-only n 0x0 0x0 BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only NREPLY No Reply 8 1 read-only NYETDIS NYET token disable 17 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE TXIN Interrupt Enable 0 1 read-only UECON0CLR Endpoint Control Clear Register 0x220 32 write-only n 0x0 0x0 BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NAKINEC NAKINE Clear 4 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only NREPLYC NREPLY Clear 8 1 write-only NYETDISC NYETDIS Clear 17 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXSTPE Clear 2 1 write-only STALLEDEC STALLEDE Clear 6 1 write-only STALLRQC STALLRQ Clear 19 1 write-only TXINEC TXINE Clear 0 1 write-only UECON0SET Endpoint Control Set Register 0x1F0 32 write-only n 0x0 0x0 BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only KILLBKS KILLBK Set 13 1 write-only NAKINES NAKINE Set 4 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only NREPLYS NREPLY Set 8 1 write-only NYETDISS NYETDIS Set 17 1 write-only RAMACERES RAMACERE Set 11 1 write-only RSTDTS RSTDT Set 18 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only STALLEDES STALLEDE Set 6 1 write-only STALLRQS STALLRQ Set 19 1 write-only TXINES TXINE Set 0 1 write-only UECON1 Endpoint Control Register 0x1C4 32 read-only n 0x0 0x0 BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only NREPLY No Reply 8 1 read-only NYETDIS NYET Token Enable 17 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE TXIN Interrupt Enable 0 1 read-only UECON1CLR TXINE Clear 0x224 32 write-only n 0x0 0x0 BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NAKINEC NAKINE Clear 4 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only NREPLYC NREPLY Clear 8 1 write-only NYETDISC NYETDIS Clear 17 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only STALLRQC STALLEDE Clear 19 1 write-only TXINEC TXINE Clear 0 1 write-only UECON1SET Endpoint Control Set Register 0x1F4 32 write-only n 0x0 0x0 BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only KILLBKS KILLBK Set 13 1 write-only NAKINES NAKINE Set 4 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only NREPLYS NREPLY Set 8 1 write-only NYETDISS NYETDIS Set 17 1 write-only RAMACERES RAMACERE Set 11 1 write-only RSTDTS RSTDT Set 18 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only STALLEDES STALLEDE Set 6 1 write-only STALLRQS STALLRQ Set 19 1 write-only TXINES TXINE Set 0 1 write-only UECON2 Endpoint Control Register 0x1C8 32 read-only n 0x0 0x0 BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only NREPLY No Reply 8 1 read-only NYETDIS NYET Token Enable 17 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE TXIN Interrupt Enable 0 1 read-only UECON2CLR TXINE Clear 0x228 32 write-only n 0x0 0x0 BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NAKINEC NAKINE Clear 4 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only NREPLYC NREPLY Clear 8 1 write-only NYETDISC NYETDIS Clear 17 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only STALLRQC STALLEDE Clear 19 1 write-only TXINEC TXINE Clear 0 1 write-only UECON2SET Endpoint Control Set Register 0x1F8 32 write-only n 0x0 0x0 BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only KILLBKS KILLBK Set 13 1 write-only NAKINES NAKINE Set 4 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only NREPLYS NREPLY Set 8 1 write-only NYETDISS NYETDIS Set 17 1 write-only RAMACERES RAMACERE Set 11 1 write-only RSTDTS RSTDT Set 18 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only STALLEDES STALLEDE Set 6 1 write-only STALLRQS STALLRQ Set 19 1 write-only TXINES TXINE Set 0 1 write-only UECON3 Endpoint Control Register 0x1CC 32 read-only n 0x0 0x0 BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only NREPLY No Reply 8 1 read-only NYETDIS NYET Token Enable 17 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE TXIN Interrupt Enable 0 1 read-only UECON3CLR TXINE Clear 0x22C 32 write-only n 0x0 0x0 BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NAKINEC NAKINE Clear 4 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only NREPLYC NREPLY Clear 8 1 write-only NYETDISC NYETDIS Clear 17 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only STALLRQC STALLEDE Clear 19 1 write-only TXINEC TXINE Clear 0 1 write-only UECON3SET Endpoint Control Set Register 0x1FC 32 write-only n 0x0 0x0 BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only KILLBKS KILLBK Set 13 1 write-only NAKINES NAKINE Set 4 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only NREPLYS NREPLY Set 8 1 write-only NYETDISS NYETDIS Set 17 1 write-only RAMACERES RAMACERE Set 11 1 write-only RSTDTS RSTDT Set 18 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only STALLEDES STALLEDE Set 6 1 write-only STALLRQS STALLRQ Set 19 1 write-only TXINES TXINE Set 0 1 write-only UECON4 Endpoint Control Register 0x1D0 32 read-only n 0x0 0x0 BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only NREPLY No Reply 8 1 read-only NYETDIS NYET Token Enable 17 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE TXIN Interrupt Enable 0 1 read-only UECON4CLR TXINE Clear 0x230 32 write-only n 0x0 0x0 BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NAKINEC NAKINE Clear 4 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only NREPLYC NREPLY Clear 8 1 write-only NYETDISC NYETDIS Clear 17 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only STALLRQC STALLEDE Clear 19 1 write-only TXINEC TXINE Clear 0 1 write-only UECON4SET Endpoint Control Set Register 0x200 32 write-only n 0x0 0x0 BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only KILLBKS KILLBK Set 13 1 write-only NAKINES NAKINE Set 4 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only NREPLYS NREPLY Set 8 1 write-only NYETDISS NYETDIS Set 17 1 write-only RAMACERES RAMACERE Set 11 1 write-only RSTDTS RSTDT Set 18 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only STALLEDES STALLEDE Set 6 1 write-only STALLRQS STALLRQ Set 19 1 write-only TXINES TXINE Set 0 1 write-only UECON5 Endpoint Control Register 0x1D4 32 read-only n 0x0 0x0 BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only NREPLY No Reply 8 1 read-only NYETDIS NYET Token Enable 17 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE TXIN Interrupt Enable 0 1 read-only UECON5CLR TXINE Clear 0x234 32 write-only n 0x0 0x0 BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NAKINEC NAKINE Clear 4 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only NREPLYC NREPLY Clear 8 1 write-only NYETDISC NYETDIS Clear 17 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only STALLRQC STALLEDE Clear 19 1 write-only TXINEC TXINE Clear 0 1 write-only UECON5SET Endpoint Control Set Register 0x204 32 write-only n 0x0 0x0 BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only KILLBKS KILLBK Set 13 1 write-only NAKINES NAKINE Set 4 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only NREPLYS NREPLY Set 8 1 write-only NYETDISS NYETDIS Set 17 1 write-only RAMACERES RAMACERE Set 11 1 write-only RSTDTS RSTDT Set 18 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only STALLEDES STALLEDE Set 6 1 write-only STALLRQS STALLRQ Set 19 1 write-only TXINES TXINE Set 0 1 write-only UECON6 Endpoint Control Register 0x1D8 32 read-only n 0x0 0x0 BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only NREPLY No Reply 8 1 read-only NYETDIS NYET Token Enable 17 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE TXIN Interrupt Enable 0 1 read-only UECON6CLR TXINE Clear 0x238 32 write-only n 0x0 0x0 BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NAKINEC NAKINE Clear 4 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only NREPLYC NREPLY Clear 8 1 write-only NYETDISC NYETDIS Clear 17 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only STALLRQC STALLEDE Clear 19 1 write-only TXINEC TXINE Clear 0 1 write-only UECON6SET Endpoint Control Set Register 0x208 32 write-only n 0x0 0x0 BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only KILLBKS KILLBK Set 13 1 write-only NAKINES NAKINE Set 4 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only NREPLYS NREPLY Set 8 1 write-only NYETDISS NYETDIS Set 17 1 write-only RAMACERES RAMACERE Set 11 1 write-only RSTDTS RSTDT Set 18 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only STALLEDES STALLEDE Set 6 1 write-only STALLRQS STALLRQ Set 19 1 write-only TXINES TXINE Set 0 1 write-only UECON7 Endpoint Control Register 0x1DC 32 read-only n 0x0 0x0 BUSY0 Busy Bank1 Enable 24 1 read-only BUSY1 Busy Bank0 Enable 25 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKIN Interrupt Enable 4 1 read-only NAKOUTE NAKOUT Interrupt Enable 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only NREPLY No Reply 8 1 read-only NYETDIS NYET Token Enable 17 1 read-only RAMACERE RAMACER Interrupt Enable 11 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE RXOUT Interrupt Enable 1 1 read-only RXSTPE RXSTP Interrupt Enable 2 1 read-only STALLEDE STALLED Interrupt Enable 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE TXIN Interrupt Enable 0 1 read-only UECON7CLR TXINE Clear 0x23C 32 write-only n 0x0 0x0 BUSY0C BUSY0 Clear 24 1 write-only BUSY1C BUSY1 Clear 25 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only NAKINEC NAKINE Clear 4 1 write-only NAKOUTEC NAKOUTE Clear 3 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only NREPLYC NREPLY Clear 8 1 write-only NYETDISC NYETDIS Clear 17 1 write-only RAMACEREC RAMACERE Clear 11 1 write-only RXOUTEC RXOUTE Clear 1 1 write-only RXSTPEC RXOUTE Clear 2 1 write-only STALLEDEC RXSTPE Clear 6 1 write-only STALLRQC STALLEDE Clear 19 1 write-only TXINEC TXINE Clear 0 1 write-only UECON7SET Endpoint Control Set Register 0x20C 32 write-only n 0x0 0x0 BUSY0S BUSY0 Set 24 1 write-only BUSY1S BUSY1 Set 25 1 write-only KILLBKS KILLBK Set 13 1 write-only NAKINES NAKINE Set 4 1 write-only NAKOUTES NAKOUTE Set 3 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only NREPLYS NREPLY Set 8 1 write-only NYETDISS NYETDIS Set 17 1 write-only RAMACERES RAMACERE Set 11 1 write-only RSTDTS RSTDT Set 18 1 write-only RXOUTES RXOUTE Set 1 1 write-only RXSTPES RXSTPE Set 2 1 write-only STALLEDES STALLEDE Set 6 1 write-only STALLRQS STALLRQ Set 19 1 write-only TXINES TXINE Set 0 1 write-only UERST Endpoint Enable/Reset Register 0x1C 32 read-write n 0x0 0x0 EPEN0 Endpoint0 Enable 0 1 EPEN1 Endpoint1 Enable 1 1 EPEN2 Endpoint2 Enable 2 1 EPEN3 Endpoint3 Enable 3 1 EPEN4 Endpoint4 Enable 4 1 EPEN5 Endpoint5 Enable 5 1 EPEN6 Endpoint6 Enable 6 1 EPEN7 Endpoint7 Enable 7 1 UESTA0 Endpoint Status Register 0x130 32 read-only n 0x0 0x0 CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT None 0x0 IN None 0x1 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only UESTA0CLR Endpoint Status Clear Register 0x160 32 write-only n 0x0 0x0 NAKINIC NAKINI Clear 4 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only TXINIC TXINI Clear 0 1 write-only UESTA0SET Endpoint Status Set Register 0x190 32 write-only n 0x0 0x0 NAKINIS NAKINI Set 4 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only RAMACERIS RAMACERI Set 11 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only STALLEDIS STALLEDI Set 6 1 write-only TXINIS TXINI Set 0 1 write-only UESTA1 Endpoint Status Register 0x134 32 read-only n 0x0 0x0 CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT None 0x0 IN None 0x1 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only UESTA1CLR Endpoint Status Clear Register 0x164 32 write-only n 0x0 0x0 NAKINIC NAKINI Clear 4 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only TXINIC TXINI Clear 0 1 write-only UESTA1SET Endpoint Status Set Register 0x194 32 write-only n 0x0 0x0 NAKINIS NAKINI Set 4 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only RAMACERIS RAMACERI Set 11 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only STALLEDIS STALLEDI Set 6 1 write-only TXINIS TXINI Set 0 1 write-only UESTA2 Endpoint Status Register 0x138 32 read-only n 0x0 0x0 CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT None 0x0 IN None 0x1 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only UESTA2CLR Endpoint Status Clear Register 0x168 32 write-only n 0x0 0x0 NAKINIC NAKINI Clear 4 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only TXINIC TXINI Clear 0 1 write-only UESTA2SET Endpoint Status Set Register 0x198 32 write-only n 0x0 0x0 NAKINIS NAKINI Set 4 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only RAMACERIS RAMACERI Set 11 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only STALLEDIS STALLEDI Set 6 1 write-only TXINIS TXINI Set 0 1 write-only UESTA3 Endpoint Status Register 0x13C 32 read-only n 0x0 0x0 CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT None 0x0 IN None 0x1 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only UESTA3CLR Endpoint Status Clear Register 0x16C 32 write-only n 0x0 0x0 NAKINIC NAKINI Clear 4 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only TXINIC TXINI Clear 0 1 write-only UESTA3SET Endpoint Status Set Register 0x19C 32 write-only n 0x0 0x0 NAKINIS NAKINI Set 4 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only RAMACERIS RAMACERI Set 11 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only STALLEDIS STALLEDI Set 6 1 write-only TXINIS TXINI Set 0 1 write-only UESTA4 Endpoint Status Register 0x140 32 read-only n 0x0 0x0 CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT None 0x0 IN None 0x1 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only UESTA4CLR Endpoint Status Clear Register 0x170 32 write-only n 0x0 0x0 NAKINIC NAKINI Clear 4 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only TXINIC TXINI Clear 0 1 write-only UESTA4SET Endpoint Status Set Register 0x1A0 32 write-only n 0x0 0x0 NAKINIS NAKINI Set 4 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only RAMACERIS RAMACERI Set 11 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only STALLEDIS STALLEDI Set 6 1 write-only TXINIS TXINI Set 0 1 write-only UESTA5 Endpoint Status Register 0x144 32 read-only n 0x0 0x0 CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT None 0x0 IN None 0x1 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only UESTA5CLR Endpoint Status Clear Register 0x174 32 write-only n 0x0 0x0 NAKINIC NAKINI Clear 4 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only TXINIC TXINI Clear 0 1 write-only UESTA5SET Endpoint Status Set Register 0x1A4 32 write-only n 0x0 0x0 NAKINIS NAKINI Set 4 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only RAMACERIS RAMACERI Set 11 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only STALLEDIS STALLEDI Set 6 1 write-only TXINIS TXINI Set 0 1 write-only UESTA6 Endpoint Status Register 0x148 32 read-only n 0x0 0x0 CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT None 0x0 IN None 0x1 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only UESTA6CLR Endpoint Status Clear Register 0x178 32 write-only n 0x0 0x0 NAKINIC NAKINI Clear 4 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only TXINIC TXINI Clear 0 1 write-only UESTA6SET Endpoint Status Set Register 0x1A8 32 write-only n 0x0 0x0 NAKINIS NAKINI Set 4 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only RAMACERIS RAMACERI Set 11 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only STALLEDIS STALLEDI Set 6 1 write-only TXINIS TXINI Set 0 1 write-only UESTA7 Endpoint Status Register 0x14C 32 read-only n 0x0 0x0 CTRLDIR Control Direction 17 1 read-only CTRLDIRSelect OUT None 0x0 IN None 0x1 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number Of Busy Banks 12 2 read-only RAMACERI Ram Access Error Interrupt 11 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only UESTA7CLR Endpoint Status Clear Register 0x17C 32 write-only n 0x0 0x0 NAKINIC NAKINI Clear 4 1 write-only NAKOUTIC NAKOUTI Clear 3 1 write-only RAMACERIC RAMACERI Clear 11 1 write-only RXOUTIC RXOUTI Clear 1 1 write-only RXSTPIC RXSTPI Clear 2 1 write-only STALLEDIC STALLEDI Clear 6 1 write-only TXINIC TXINI Clear 0 1 write-only UESTA7SET Endpoint Status Set Register 0x1AC 32 write-only n 0x0 0x0 NAKINIS NAKINI Set 4 1 write-only NAKOUTIS NAKOUTI Set 3 1 write-only NBUSYBKS NBUSYBK Set 12 1 write-only RAMACERIS RAMACERI Set 11 1 write-only RXOUTIS RXOUTI Set 1 1 write-only RXSTPIS RXSTPI Set 2 1 write-only STALLEDIS STALLEDI Set 6 1 write-only TXINIS TXINI Set 0 1 write-only UFEATURES IP Features Register 0x81C 32 read-only n 0x0 0x0 EPTNBRMAX Maximum Number of Pipes/Endpints 0 4 read-only UTMIMODE UTMI Mode 8 1 read-only UHCON Host General Control Register 0x400 32 read-write n 0x0 0x0 RESET Send USB Reset 9 1 RESUME Send USB Resume 10 1 SOFE SOF Enable 8 1 SPDCONF Speed Configuration 12 2 TSTJ Test J 16 1 TSTK Test K 17 1 UHFNUM Host Frame Number Register 0x420 32 read-write n 0x0 0x0 FLENHIGH Frame Length 16 8 read-only FNUM Frame Number 3 11 MFNUM Micro Frame Number 0 3 read-only UHINT Host Global Interrupt Register 0x404 32 read-only n 0x0 0x0 DCONNI Device Connection Interrupt 0 1 read-only DDISCI Device Disconnection Interrupt 1 1 read-only HSOFI Host SOF Interrupt 5 1 read-only HWUPI Host Wake-Up Interrupt 6 1 read-only P0INT Pipe 0 Interrupt 8 1 read-only P1INT Pipe 1 Interrupt 9 1 read-only P2INT Pipe 2 Interrupt 10 1 read-only P3INT Pipe 3 Interrupt 11 1 read-only P4INT Pipe 4 Interrupt 12 1 read-only P5INT Pipe 5 Interrupt 13 1 read-only P6INT Pipe 6 Interrupt 14 1 read-only RSMEDI Downstream Resume Sent Interrupt 3 1 read-only RSTI USB Reset Sent Interrupt 2 1 read-only RXRSMI Upstream Resume Received Interrupt 4 1 read-only UHINTCLR Host Global Interrrupt Clear Register 0x408 32 write-only n 0x0 0x0 DCONNIC DCONNI Clear 0 1 write-only DDISCIC DDISCI Clear 1 1 write-only HSOFIC HSOFI Clear 5 1 write-only HWUPIC HWUPI Clear 6 1 write-only RSMEDIC RSMEDI Clear 3 1 write-only RSTIC RSTI Clear 2 1 write-only RXRSMIC RXRSMI Clear 4 1 write-only UHINTE Host Global Interrupt Enable Register 0x410 32 read-only n 0x0 0x0 DCONNIE DCONNI Enable 0 1 read-only DDISCIE DDISCI Enable 1 1 read-only HSOFIE HSOFI Enable 5 1 read-only HWUPIE HWUPI Enable 6 1 read-only P0INTE P0INT Enable 8 1 read-only P1INTE P1INT Enable 9 1 read-only P2INTE P2INT Enable 10 1 read-only P3INTE P3INT Enable 11 1 read-only P4INTE P4INT Enable 12 1 read-only P5INTE P5INT Enable 13 1 read-only P6INTE P6INT Enable 14 1 read-only P7INTE P7INT Enable 15 1 read-only RSMEDIE RSMEDI Enable 3 1 read-only RSTIE RSTI Enable 2 1 read-only RXRSMIE RXRSMI Enable 4 1 read-only UHINTECLR Host Global Interrupt Enable Clear Register 0x414 32 write-only n 0x0 0x0 DCONNIEC DCONNIE Clear 0 1 write-only DDISCIEC DDISCIE Clear 1 1 write-only HSOFIEC HSOFIE Clear 5 1 write-only HWUPIEC HWUPIE Clear 6 1 write-only P0INTEC P0INTE Clear 8 1 write-only P1INTEC P1INTE Clear 9 1 write-only P2INTEC P2INTE Clear 10 1 write-only P3INTEC P3INTE Clear 11 1 write-only P4INTEC P4INTE Clear 12 1 write-only P5INTEC P5INTE Clear 13 1 write-only P6INTEC P6INTE Clear 14 1 write-only P7INTEC P7INTE Clear 15 1 write-only RSMEDIEC RSMEDIE Clear 3 1 write-only RSTIEC RSTIE Clear 2 1 write-only RXRSMIEC RXRSMIE Clear 4 1 write-only UHINTESET Host Global Interrupt Enable Set Register 0x418 32 write-only n 0x0 0x0 DCONNIES DCONNIE Set 0 1 write-only DDISCIES DDISCIE Set 1 1 write-only HSOFIES HSOFIE Set 5 1 write-only HWUPIES HWUPIE Set 6 1 write-only P0INTES P0INTE Set 8 1 write-only P1INTES P1INTE Set 9 1 write-only P2INTES P2INTE Set 10 1 write-only P3INTES P3INTE Set 11 1 write-only P4INTES P4INTE Set 12 1 write-only P5INTES P5INTE Set 13 1 write-only P6INTES P6INTE Set 14 1 write-only P7INTES P7INTE Set 15 1 write-only RSMEDIES RSMEDIE Set 3 1 write-only RSTIES RSTIE Set 2 1 write-only RXRSMIES RXRSMIE Set 4 1 write-only UHINTSET Host Global Interrupt Set Register 0x40C 32 write-only n 0x0 0x0 DCONNIS DCONNI Set 0 1 write-only DDISCIS DDISCI Set 1 1 write-only HSOFIS HSOFI Set 5 1 write-only HWUPIS HWUPI Set 6 1 write-only RSMEDIS RSMEDI Set 3 1 write-only RSTIS RSTI Set 2 1 write-only RXRSMIS RXRSMI Set 4 1 write-only UHSOFC Host Start of Frame Control Register 0x424 32 read-write n 0x0 0x0 FLENC Frame Length Control 0 14 FLENCE Frame Length Control Enable 16 1 UNAME1 IP Name Part One: HUSB 0x824 32 read-only n 0x0 0x0 UNAME1 IP Name Part One 0 32 UNAME2 IP Name Part Two: HOST 0x828 32 read-only n 0x0 0x0 UNAME2 IP Name Part Two 0 32 UPCFG0 Pipe Configuration Register 0x500 32 read-write n 0x0 0x0 BINTERVAL binterval parameter 24 8 PBK Pipe Banks 2 1 PBKSelect SINGLE None 0x0 DOUBLE None 0x1 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP None 0x0 IN None 0x1 OUT None 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 UPCFG1 Pipe Configuration Register 0x504 32 read-write n 0x0 0x0 BINTERVAL binterval parameter 24 8 PBK Pipe Banks 2 1 PBKSelect SINGLE None 0x0 DOUBLE None 0x1 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP None 0x0 IN None 0x1 OUT None 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 UPCFG2 Pipe Configuration Register 0x508 32 read-write n 0x0 0x0 BINTERVAL binterval parameter 24 8 PBK Pipe Banks 2 1 PBKSelect SINGLE None 0x0 DOUBLE None 0x1 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP None 0x0 IN None 0x1 OUT None 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 UPCFG3 Pipe Configuration Register 0x50C 32 read-write n 0x0 0x0 BINTERVAL binterval parameter 24 8 PBK Pipe Banks 2 1 PBKSelect SINGLE None 0x0 DOUBLE None 0x1 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP None 0x0 IN None 0x1 OUT None 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 UPCFG4 Pipe Configuration Register 0x510 32 read-write n 0x0 0x0 BINTERVAL binterval parameter 24 8 PBK Pipe Banks 2 1 PBKSelect SINGLE None 0x0 DOUBLE None 0x1 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP None 0x0 IN None 0x1 OUT None 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 UPCFG5 Pipe Configuration Register 0x514 32 read-write n 0x0 0x0 BINTERVAL binterval parameter 24 8 PBK Pipe Banks 2 1 PBKSelect SINGLE None 0x0 DOUBLE None 0x1 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP None 0x0 IN None 0x1 OUT None 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 UPCFG6 Pipe Configuration Register 0x518 32 read-write n 0x0 0x0 BINTERVAL binterval parameter 24 8 PBK Pipe Banks 2 1 PBKSelect SINGLE None 0x0 DOUBLE None 0x1 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP None 0x0 IN None 0x1 OUT None 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 UPCFG7 Pipe Configuration Register 0x51C 32 read-write n 0x0 0x0 BINTERVAL binterval parameter 24 8 PBK Pipe Banks 2 1 PBKSelect SINGLE None 0x0 DOUBLE None 0x1 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect 8 None 0x0 16 None 0x1 32 None 0x2 64 None 0x3 128 None 0x4 256 None 0x5 512 None 0x6 1024 None 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP None 0x0 IN None 0x1 OUT None 0x2 PTYPE Pipe Type 12 2 PTYPESelect CONTROL None 0x0 ISOCHRONOUS None 0x1 BULK None 0x2 INTERRUPT None 0x3 UPCON0 Pipe Control Register 0x5C0 32 read-only n 0x0 0x0 ERRORFIE ERRORFI Interrupt Enable 5 1 read-only FIFOCON FIFO Control 14 1 read-only INITBK Bank Initialization 19 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only PERRE PERR Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only RXINE RXIN Interrupt Enable 0 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only UPCON0CLR Pipe Control Clear Register 0x620 32 write-only n 0x0 0x0 ERRORFIEC ERRORFIE Clear 5 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only INITBKC INITBK Clear 19 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only NAKEDEC NAKEDE Clear 4 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only PERREC PERRE Clear 3 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only RXINEC RXINE Clear 0 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only UPCON0SET Pipe Control Set Register 0x5F0 32 write-only n 0x0 0x0 ERRORFIES ERRORFIE Set 5 1 write-only FIFOCONS FIFOCON Set 14 1 write-only INITBKS INITBK Set 19 1 write-only INITDTGLS INITDTGL Set 18 1 write-only NAKEDES NAKEDE Set 4 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only PERRES PERRE Set 3 1 write-only PFREEZES PFREEZE Set 17 1 write-only RAMACERES RAMACERE Set 10 1 write-only RXINES RXINE Set 0 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only UPCON1 Pipe Control Register 0x5C4 32 read-only n 0x0 0x0 ERRORFIE ERRORFI Interrupt Enable 5 1 read-only FIFOCON FIFO Control 14 1 read-only INITBK Bank Initialization 19 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only PERRE PERR Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only RXINE RXIN Interrupt Enable 0 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only UPCON1CLR Pipe Control Clear Register 0x624 32 write-only n 0x0 0x0 ERRORFIEC ERRORFIE Clear 5 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only INITBKC INITBK Clear 19 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only NAKEDEC NAKEDE Clear 4 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only PERREC PERRE Clear 3 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only RXINEC RXINE Clear 0 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only UPCON1SET Pipe Control Set Register 0x5F4 32 write-only n 0x0 0x0 ERRORFIES ERRORFIE Set 5 1 write-only FIFOCONS FIFOCON Set 14 1 write-only INITBKS INITBK Set 19 1 write-only INITDTGLS INITDTGL Set 18 1 write-only NAKEDES NAKEDE Set 4 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only PERRES PERRE Set 3 1 write-only PFREEZES PFREEZE Set 17 1 write-only RAMACERES RAMACERE Set 10 1 write-only RXINES RXINE Set 0 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only UPCON2 Pipe Control Register 0x5C8 32 read-only n 0x0 0x0 ERRORFIE ERRORFI Interrupt Enable 5 1 read-only FIFOCON FIFO Control 14 1 read-only INITBK Bank Initialization 19 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only PERRE PERR Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only RXINE RXIN Interrupt Enable 0 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only UPCON2CLR Pipe Control Clear Register 0x628 32 write-only n 0x0 0x0 ERRORFIEC ERRORFIE Clear 5 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only INITBKC INITBK Clear 19 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only NAKEDEC NAKEDE Clear 4 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only PERREC PERRE Clear 3 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only RXINEC RXINE Clear 0 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only UPCON2SET Pipe Control Set Register 0x5F8 32 write-only n 0x0 0x0 ERRORFIES ERRORFIE Set 5 1 write-only FIFOCONS FIFOCON Set 14 1 write-only INITBKS INITBK Set 19 1 write-only INITDTGLS INITDTGL Set 18 1 write-only NAKEDES NAKEDE Set 4 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only PERRES PERRE Set 3 1 write-only PFREEZES PFREEZE Set 17 1 write-only RAMACERES RAMACERE Set 10 1 write-only RXINES RXINE Set 0 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only UPCON3 Pipe Control Register 0x5CC 32 read-only n 0x0 0x0 ERRORFIE ERRORFI Interrupt Enable 5 1 read-only FIFOCON FIFO Control 14 1 read-only INITBK Bank Initialization 19 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only PERRE PERR Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only RXINE RXIN Interrupt Enable 0 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only UPCON3CLR Pipe Control Clear Register 0x62C 32 write-only n 0x0 0x0 ERRORFIEC ERRORFIE Clear 5 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only INITBKC INITBK Clear 19 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only NAKEDEC NAKEDE Clear 4 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only PERREC PERRE Clear 3 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only RXINEC RXINE Clear 0 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only UPCON3SET Pipe Control Set Register 0x5FC 32 write-only n 0x0 0x0 ERRORFIES ERRORFIE Set 5 1 write-only FIFOCONS FIFOCON Set 14 1 write-only INITBKS INITBK Set 19 1 write-only INITDTGLS INITDTGL Set 18 1 write-only NAKEDES NAKEDE Set 4 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only PERRES PERRE Set 3 1 write-only PFREEZES PFREEZE Set 17 1 write-only RAMACERES RAMACERE Set 10 1 write-only RXINES RXINE Set 0 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only UPCON4 Pipe Control Register 0x5D0 32 read-only n 0x0 0x0 ERRORFIE ERRORFI Interrupt Enable 5 1 read-only FIFOCON FIFO Control 14 1 read-only INITBK Bank Initialization 19 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only PERRE PERR Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only RXINE RXIN Interrupt Enable 0 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only UPCON4CLR Pipe Control Clear Register 0x630 32 write-only n 0x0 0x0 ERRORFIEC ERRORFIE Clear 5 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only INITBKC INITBK Clear 19 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only NAKEDEC NAKEDE Clear 4 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only PERREC PERRE Clear 3 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only RXINEC RXINE Clear 0 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only UPCON4SET Pipe Control Set Register 0x600 32 write-only n 0x0 0x0 ERRORFIES ERRORFIE Set 5 1 write-only FIFOCONS FIFOCON Set 14 1 write-only INITBKS INITBK Set 19 1 write-only INITDTGLS INITDTGL Set 18 1 write-only NAKEDES NAKEDE Set 4 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only PERRES PERRE Set 3 1 write-only PFREEZES PFREEZE Set 17 1 write-only RAMACERES RAMACERE Set 10 1 write-only RXINES RXINE Set 0 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only UPCON5 Pipe Control Register 0x5D4 32 read-only n 0x0 0x0 ERRORFIE ERRORFI Interrupt Enable 5 1 read-only FIFOCON FIFO Control 14 1 read-only INITBK Bank Initialization 19 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only PERRE PERR Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only RXINE RXIN Interrupt Enable 0 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only UPCON5CLR Pipe Control Clear Register 0x634 32 write-only n 0x0 0x0 ERRORFIEC ERRORFIE Clear 5 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only INITBKC INITBK Clear 19 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only NAKEDEC NAKEDE Clear 4 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only PERREC PERRE Clear 3 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only RXINEC RXINE Clear 0 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only UPCON5SET Pipe Control Set Register 0x604 32 write-only n 0x0 0x0 ERRORFIES ERRORFIE Set 5 1 write-only FIFOCONS FIFOCON Set 14 1 write-only INITBKS INITBK Set 19 1 write-only INITDTGLS INITDTGL Set 18 1 write-only NAKEDES NAKEDE Set 4 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only PERRES PERRE Set 3 1 write-only PFREEZES PFREEZE Set 17 1 write-only RAMACERES RAMACERE Set 10 1 write-only RXINES RXINE Set 0 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only UPCON6 Pipe Control Register 0x5D8 32 read-only n 0x0 0x0 ERRORFIE ERRORFI Interrupt Enable 5 1 read-only FIFOCON FIFO Control 14 1 read-only INITBK Bank Initialization 19 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only PERRE PERR Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only RXINE RXIN Interrupt Enable 0 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only UPCON6CLR Pipe Control Clear Register 0x638 32 write-only n 0x0 0x0 ERRORFIEC ERRORFIE Clear 5 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only INITBKC INITBK Clear 19 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only NAKEDEC NAKEDE Clear 4 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only PERREC PERRE Clear 3 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only RXINEC RXINE Clear 0 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only UPCON6SET Pipe Control Set Register 0x608 32 write-only n 0x0 0x0 ERRORFIES ERRORFIE Set 5 1 write-only FIFOCONS FIFOCON Set 14 1 write-only INITBKS INITBK Set 19 1 write-only INITDTGLS INITDTGL Set 18 1 write-only NAKEDES NAKEDE Set 4 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only PERRES PERRE Set 3 1 write-only PFREEZES PFREEZE Set 17 1 write-only RAMACERES RAMACERE Set 10 1 write-only RXINES RXINE Set 0 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only UPCON7 Pipe Control Register 0x5DC 32 read-only n 0x0 0x0 ERRORFIE ERRORFI Interrupt Enable 5 1 read-only FIFOCON FIFO Control 14 1 read-only INITBK Bank Initialization 19 1 read-only INITDTGL Data Toggle Initialization 18 1 read-only NAKEDE NAKED Interrupt Enable 4 1 read-only NBUSYBKE NBUSYBKInterrupt Enable 12 1 read-only PERRE PERR Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RAMACERE RAMACER Interrupt Enable 10 1 read-only RXINE RXIN Interrupt Enable 0 1 read-only RXSTALLDE RXTALLD Interrupt Enable 6 1 read-only TXOUTE TXOUT Interrupt Enable 1 1 read-only TXSTPE TXSTP Interrupt Enable 2 1 read-only UPCON7CLR Pipe Control Clear Register 0x63C 32 write-only n 0x0 0x0 ERRORFIEC ERRORFIE Clear 5 1 write-only FIFOCONC FIFOCON Clear 14 1 write-only INITBKC INITBK Clear 19 1 write-only INITDTGLC INITDTGL Clear 18 1 read-only NAKEDEC NAKEDE Clear 4 1 write-only NBUSYBKEC NBUSYBKE Clear 12 1 write-only PERREC PERRE Clear 3 1 write-only PFREEZEC PFREEZE Clear 17 1 write-only RAMACEREC RAMACERE Clear 10 1 write-only RXINEC RXINE Clear 0 1 write-only RXSTALLDEC RXTALLDE Clear 6 1 write-only TXOUTEC TXOUTE Clear 1 1 write-only TXSTPEC TXSTPE Clear 2 1 write-only UPCON7SET Pipe Control Set Register 0x60C 32 write-only n 0x0 0x0 ERRORFIES ERRORFIE Set 5 1 write-only FIFOCONS FIFOCON Set 14 1 write-only INITBKS INITBK Set 19 1 write-only INITDTGLS INITDTGL Set 18 1 write-only NAKEDES NAKEDE Set 4 1 write-only NBUSYBKES NBUSYBKE Set 12 1 write-only PERRES PERRE Set 3 1 write-only PFREEZES PFREEZE Set 17 1 write-only RAMACERES RAMACERE Set 10 1 write-only RXINES RXINE Set 0 1 write-only RXSTALLDES RXSTALLDE Set 6 1 write-only TXOUTES TXOUTE Set 1 1 write-only TXSTPES TXSTPE Set 2 1 write-only UPINRQ0 Pipe In Request 0x650 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 UPINRQ1 Pipe In Request 0x654 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 UPINRQ2 Pipe In Request 0x658 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 UPINRQ3 Pipe In Request 0x65C 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 UPINRQ4 Pipe In Request 0x660 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 UPINRQ5 Pipe In Request 0x664 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 UPINRQ6 Pipe In Request 0x668 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 UPINRQ7 Pipe In Request 0x66C 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 UPRST Pipe Reset Register 0x41C 32 read-write n 0x0 0x0 PEN0 Pipe0 Enable 0 1 PEN1 Pipe1 Enable 1 1 PEN2 Pipe2 Enable 2 1 PEN3 Pipe3 Enable 3 1 PEN4 Pipe4 Enable 4 1 PEN5 Pipe5 Enable 5 1 PEN6 Pipe6 Enable 6 1 PEN7 Pipe7 Enable 7 1 UPSTA0 Pipe Status Register 0x530 32 read-only n 0x0 0x0 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only ERRORFI Errorflow Interrupt 5 1 read-only NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only PERRI Pipe Error Interrupt 3 1 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only UPSTA0CLR Pipe Status Clear Register 0x560 32 write-only n 0x0 0x0 ERRORFIC ERRORFI Clear 5 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only PERRIC PERRI Clear 3 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only RXINIC RXINI Clear 0 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only UPSTA0SET Pipe Status Set Register 0x590 32 write-only n 0x0 0x0 ERRORFIS ERRORFI Set 5 1 write-only NAKEDIS NAKEDI Set 4 1 write-only PERRIS PERRI Set 3 1 write-only RAMACERIS RAMACERI Set 10 1 write-only RXINIS RXINI Set 0 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only UPSTA1 Pipe Status Register 0x534 32 read-only n 0x0 0x0 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only ERRORFI Errorflow Interrupt 5 1 read-only NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only PERRI Pipe Error Interrupt 3 1 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only UPSTA1CLR Pipe Status Clear Register 0x564 32 write-only n 0x0 0x0 ERRORFIC ERRORFI Clear 5 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only PERRIC PERRI Clear 3 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only RXINIC RXINI Clear 0 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only UPSTA1SET Pipe Status Set Register 0x594 32 write-only n 0x0 0x0 ERRORFIS ERRORFI Set 5 1 write-only NAKEDIS NAKEDI Set 4 1 write-only PERRIS PERRI Set 3 1 write-only RAMACERIS RAMACERI Set 10 1 write-only RXINIS RXINI Set 0 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only UPSTA2 Pipe Status Register 0x538 32 read-only n 0x0 0x0 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only ERRORFI Errorflow Interrupt 5 1 read-only NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only PERRI Pipe Error Interrupt 3 1 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only UPSTA2CLR Pipe Status Clear Register 0x568 32 write-only n 0x0 0x0 ERRORFIC ERRORFI Clear 5 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only PERRIC PERRI Clear 3 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only RXINIC RXINI Clear 0 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only UPSTA2SET Pipe Status Set Register 0x598 32 write-only n 0x0 0x0 ERRORFIS ERRORFI Set 5 1 write-only NAKEDIS NAKEDI Set 4 1 write-only PERRIS PERRI Set 3 1 write-only RAMACERIS RAMACERI Set 10 1 write-only RXINIS RXINI Set 0 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only UPSTA3 Pipe Status Register 0x53C 32 read-only n 0x0 0x0 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only ERRORFI Errorflow Interrupt 5 1 read-only NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only PERRI Pipe Error Interrupt 3 1 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only UPSTA3CLR Pipe Status Clear Register 0x56C 32 write-only n 0x0 0x0 ERRORFIC ERRORFI Clear 5 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only PERRIC PERRI Clear 3 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only RXINIC RXINI Clear 0 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only UPSTA3SET Pipe Status Set Register 0x59C 32 write-only n 0x0 0x0 ERRORFIS ERRORFI Set 5 1 write-only NAKEDIS NAKEDI Set 4 1 write-only PERRIS PERRI Set 3 1 write-only RAMACERIS RAMACERI Set 10 1 write-only RXINIS RXINI Set 0 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only UPSTA4 Pipe Status Register 0x540 32 read-only n 0x0 0x0 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only ERRORFI Errorflow Interrupt 5 1 read-only NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only PERRI Pipe Error Interrupt 3 1 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only UPSTA4CLR Pipe Status Clear Register 0x570 32 write-only n 0x0 0x0 ERRORFIC ERRORFI Clear 5 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only PERRIC PERRI Clear 3 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only RXINIC RXINI Clear 0 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only UPSTA4SET Pipe Status Set Register 0x5A0 32 write-only n 0x0 0x0 ERRORFIS ERRORFI Set 5 1 write-only NAKEDIS NAKEDI Set 4 1 write-only PERRIS PERRI Set 3 1 write-only RAMACERIS RAMACERI Set 10 1 write-only RXINIS RXINI Set 0 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only UPSTA5 Pipe Status Register 0x544 32 read-only n 0x0 0x0 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only ERRORFI Errorflow Interrupt 5 1 read-only NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only PERRI Pipe Error Interrupt 3 1 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only UPSTA5CLR Pipe Status Clear Register 0x574 32 write-only n 0x0 0x0 ERRORFIC ERRORFI Clear 5 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only PERRIC PERRI Clear 3 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only RXINIC RXINI Clear 0 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only UPSTA5SET Pipe Status Set Register 0x5A4 32 write-only n 0x0 0x0 ERRORFIS ERRORFI Set 5 1 write-only NAKEDIS NAKEDI Set 4 1 write-only PERRIS PERRI Set 3 1 write-only RAMACERIS RAMACERI Set 10 1 write-only RXINIS RXINI Set 0 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only UPSTA6 Pipe Status Register 0x548 32 read-only n 0x0 0x0 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only ERRORFI Errorflow Interrupt 5 1 read-only NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only PERRI Pipe Error Interrupt 3 1 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only UPSTA6CLR Pipe Status Clear Register 0x578 32 write-only n 0x0 0x0 ERRORFIC ERRORFI Clear 5 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only PERRIC PERRI Clear 3 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only RXINIC RXINI Clear 0 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only UPSTA6SET Pipe Status Set Register 0x5A8 32 write-only n 0x0 0x0 ERRORFIS ERRORFI Set 5 1 write-only NAKEDIS NAKEDI Set 4 1 write-only PERRIS PERRI Set 3 1 write-only RAMACERIS RAMACERI Set 10 1 write-only RXINIS RXINI Set 0 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only UPSTA7 Pipe Status Register 0x54C 32 read-only n 0x0 0x0 CURRBK Current Bank 14 2 read-only DTSEQ Data Toggle Sequence 8 2 read-only ERRORFI Errorflow Interrupt 5 1 read-only NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Bank 12 2 read-only PERRI Pipe Error Interrupt 3 1 read-only RAMACERI Ram Access Error Interrupt 10 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only UPSTA7CLR Pipe Status Clear Register 0x57C 32 write-only n 0x0 0x0 ERRORFIC ERRORFI Clear 5 1 write-only NAKEDIC NAKEDI Clear 4 1 write-only PERRIC PERRI Clear 3 1 write-only RAMACERIC RAMACERI Clear 10 1 write-only RXINIC RXINI Clear 0 1 write-only RXSTALLDIC RXSTALLDI Clear 6 1 write-only TXOUTIC TXOUTI Clear 1 1 write-only TXSTPIC TXSTPI Clear 2 1 write-only UPSTA7SET Pipe Status Set Register 0x5AC 32 write-only n 0x0 0x0 ERRORFIS ERRORFI Set 5 1 write-only NAKEDIS NAKEDI Set 4 1 write-only PERRIS PERRI Set 3 1 write-only RAMACERIS RAMACERI Set 10 1 write-only RXINIS RXINI Set 0 1 write-only RXSTALLDIS RXSTALLDI Set 6 1 write-only TXOUTIS TXOUTI Set 1 1 write-only TXSTPIS TXSTPI Set 2 1 write-only USBCON General Control Register 0x800 32 read-write n 0x0 0x0 FRZCLK Freeze USB Clock 14 1 UIMOD USBC Mode 24 1 USBE USBC Enable 15 1 USBFSM USB internal finite state machine 0x82C 32 read-only n 0x0 0x0 DRDSTATE DualRoleDevice state 0 4 read-only DRDSTATESelect A_IDLE None 0x0 A_WAIT_VRISE None 0x1 A_WAIT_BCON None 0x2 A_HOST None 0x3 A_SUSPEND None 0x4 A_PERIPHERAL None 0x5 A_WAIT_VFALL None 0x6 A_VBUS_ERR None 0x7 A_WAIT_DISCHARGE None 0x8 B_IDLE None 0x9 B_PERIPHERAL None 0xa B_WAIT_BEGIN_HNP None 0xb B_WAIT_DISCHARGE None 0xc B_WAIT_ACON None 0xd B_HOST None 0xe B_SRP_INIT None 0xf USBSTA General Status Register 0x804 32 read-only n 0x0 0x0 CLKUSABLE USB Clock Usable 14 1 read-only SPEED Speed Status 12 2 read-only SPEEDSelect FULL None 0x0 HIGH None 0x1 LOW None 0x2 SUSPEND Suspend module state 16 1 read-only VBUSRQ VBus Request 9 1 read-only USBSTACLR General Status Clear Register 0x808 32 write-only n 0x0 0x0 RAMACERIC RAMACERI Clear 8 1 write-only VBUSRQC VBUSRQ Clear 9 1 write-only USBSTASET General Status Set Register 0x80C 32 write-only n 0x0 0x0 RAMACERIS RAMACERI Set 8 1 write-only VBUSRQS VBUSRQ Set 9 1 write-only UVERS IP Version Register 0x818 32 read-only n 0x0 0x0 VARIANT Variant Number 16 3 read-only VERSION Version Number 0 12 read-only WDT Watchdog Timer WDT 0x0 0x0 0x400 registers n WDT 44 CLR Clear Register 0x4 32 write-only n 0x0 0x0 KEY Key 24 8 write-only WDTCLR Clear WDT counter 0 1 write-only CTRL Control Register 0x0 32 read-write n 0x0 0x0 CEN Clock Enable 16 1 CSSEL Clock Source Selection0 17 1 CSSEL1 Clock Source Selection1 14 1 DAR WDT Disable After Reset 1 1 EN WDT Enable 0 1 ENSelect 0 WDT is disabled. 0x0 1 WDT is enabled 0x1 FCD WDT Fuse Calibration Done 7 1 IM WDT Interruput Mode 4 1 KEY Key 24 8 MODE WDT Mode 2 1 PSEL Timeout Prescale Select 8 5 SFV WDT Store Final Value 3 1 TBAN TBAN Prescale Select 18 5 ICR Interrupt Clear Register 0x1C 32 write-only n 0x0 0x0 WINT Watchdog Interrupt 2 1 IDR Interrupt Disable Register 0x10 32 write-only n 0x0 0x0 WINT Watchdog Interrupt 2 1 IER Interrupt Enable Register 0xC 32 write-only n 0x0 0x0 WINT Watchdog Interrupt 2 1 IMR Interrupt Mask Register 0x14 32 read-only n 0x0 0x0 WINT Watchdog Interrupt 2 1 ISR Interrupt Status Register 0x18 32 read-only n 0x0 0x0 WINT Watchdog Interrupt 2 1 SR Status Register 0x8 32 read-only n 0x0 0x0 CLEARED WDT cleared 1 1 read-only WINDOW WDT in window 0 1 read-only VERSION Version Register 0x3FC 32 read-only n 0x0 0x0 VARIANT Variant number 16 4 VERSION Version number 0 12